鄢贵海  男  博导  中国科学院计算技术研究所
电子邮件: yan@ict.ac.cn
通信地址: 科学院南路6号中科院计算所
邮政编码: 100190

研究领域

计算机体系结构,智能处理器设计,金融计算。
详见个人主页www.carch.ac.cn/~yan

招生信息

   
招生专业
081201-计算机系统结构
招生方向
计算机系统结构
智能处理器设计
金融计算

教育背景

2005-07--2010-08   中国科学院计算技术研究所   博士
2001-09--2005-07   北京大学 信息科学技术学院   本科

工作经历

   
工作简历
2018-09~现在, 中国科学院计算技术研究所, 研究员
2013-10~2018-08,中国科学院计算技术研究所, 副研究员
2011-01~2013-09,中国科学院计算技术研究所, 助理研究员

专利与奖励

   
奖励信息
(1) 北京市科技奖, 二等奖, 市地级, 2017
(2) 中国科协优秀科技论文奖, 专项, 2017
(3) 中国计量测试学会科学技术进步奖, 二等奖, 专项, 2017
(4) 中国计算机学会优秀博士论文, , 专项, 2012
(5) 中国科学院优秀博士论文, , 院级, 2011
(6) 中国质量协会质量技术奖, 一等奖, 部委级, 2011
(7) TTTC's E.J. McCluskey Best Doctoral Thesis Award, , 其他, 2011
(8) 中国科学院院长奖学金, , 院级, 2010
(9) 计算技术研究所所长奖学金, 特等奖, 研究所(学校), 2010
专利成果
( 1 ) 一种智能移动终端功耗管理方法, 发明, 2013, 第 1 作者, 专利号: CN201310403344.2
( 2 ) 一种网络地址转换方法, 发明, 2009, 第 1 作者, 专利号: ZL200610144248.0
( 3 ) 一种宽动态工作电压范围处理器供电系统设计, 发明, 2014, 第 2 作者, 专利号: 201410535695.3
( 4 ) 一种基于信息熵的机器学习算法自适应调整方法, 发明, 2018, 第 2 作者, 专利号: CN201810008518.8
( 5 ) 一种基于集成学习的最优收敛差错控制方法和结构, 发明, 2018, 第 2 作者, 专利号: CN201810186544.X
( 6 ) 一种支持稀疏二维卷积的运算架构, 发明, 2018, 第 2 作者, 专利号: CN201810022861.8
( 7 ) 一种线性时间复杂度的布尔型时间序列最大可满足性求解的方法, 发明, 2017, 第 2 作者, 专利号: CN201711463282.9
( 8 ) 数据中心的服务器性能评估及服务器更新方法, 发明, 2016, 第 2 作者, 专利号: CN201610091361.0

出版信息

Clik http://www.carch.ac.cn/~adapt/publication.html for the full publication list.

发表论文
(1) Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks,, IEEE Transactions on Computers, 2019, 第 2 作者
(2) ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications, Proceedings of Annual Design Automation Conference, 2019, 第 4 作者
(3) TNPU: An Efficient Accelerator Architecture for Training Convolutional Neural Networks,, Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019, 第 2 作者
(4) Fault Tolerance On-Chip: A Reliable Computing Paradigm Using Self-test, Self-diagnosis, and Self-repair (3S) Approach, SCIENCE CHINA Information Sciences, 2018, 第 2 作者
(5) AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability, Journal of Low Power Electronics, 2018, 第 2 作者
(6) Optimizing Memory Efficiency for Deep Convolutional Neural Network Accelerators, Journal of Low Power Electronics, 2018, 第 3 作者
(7) Tetris: Re-architecting Convolutional Neural Network Computation for Machine Learning Accelerators, International Conference On Computer Aided Design, 2018, 第 4 作者
(8) SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks, ACM Transactions on Design Automation of Electronic Systems, 2018, 第 2 作者
(9) Exploiting the Potential of Computation Reuse Through Approximate Computing,, IEEE Transactions on Multi-Scale Computing Systems, 2017, 第 4 作者
(10) A Quantitative Analysis on the "Approximability" of Machine Learning Algorithm, Journal of Computer Reasearch and Development, 2017, 第 2 作者
(11) PowerTrader: Enforcing Autonomous Power Management for Future Large-scale Manycore Processors, IEEE Transactions on Multi-Scale Computing Systems, 2017, 第 2 作者
(12) FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks, IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, 第 2 作者
(13) Exploiting the Potential of Computation Reuse through Approximate Computing, IEEE Transactions on Multi-Scale Computing Systems, 2017, 第 3 作者
(14) CoreRank: Redeeming “Sick Silicon” by Dynamically Quantifying Core-level Healthy Condition, IEEE Transactions on Computers, 2016, 第 1 作者
(15) EcoUp: Towards Economical Datacenter Upgrading, IEEE Transactions on Parallel and Distributed Systems, 2016, 通讯作者
(16) Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing, Journal of Computer Science and Technology, 2016, 第 2 作者
(17) PowerCap Leverage Performance-equivalent Resource Configurations for Power Capping, IGSC, 2016, 第 4 作者
(18) ShuttleNoC: Boosting On-chip Communication Efficiency by Enabling Localized Power Adaptation, Asia and South Pacific Design Automation Conference, 2015, 第 2 作者
(19) An Analytical Framework for Estimating Scale-out and Scale-up Power Efficiency of Heterogeneous Manycores, IEEE Transactions on Computers, 2015, 第 2 作者
(20) RISO: Enforce Non-interfered Performance with Relaxed Network-on-Chip Isolation in Manycore Cloud Processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 通讯作者
(21) Amphisbaena: Modeling Two Orthogonal Ways to Hunt on Heterogeneous Many-cores, In the Proceedings of 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, 通讯作者
(22) SuperRange: Wide Operational Range Power Delivery Design for both STV and NTV Computing, In the Proceedings of IEEE/ACM Desing, Automation and Test in Europe (DATE), 2014, 通讯作者
(23) SmartCap: Using Machine Learning for Power Adaptation of Smartphone’s Application Processor, ACM Transactions on Design Automation of Electronic Systems, 2014, 第 2 作者
(24) On-Chip Delay Sensor for Environments with large Temperature Fluctuations, IEEE Asian Test Symposium, 2014, 第 2 作者
(25) Orchestrator: Guarding Against Voltage Emergencies in Multi-threaded Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 第 2 作者
(26) RISO: Relaxed Network-on-Chip Isolation for Cloud Processors, In the Proceedings of Design Automation Conference (DAC2013), 2013, 第 2 作者
(27) Orchestrator: a Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded Applications, In the Proceedings of IEEE/ACM Desing, Automation and Test in Europe (DATE), 2013, 第 2 作者
(28) SmartCap: User Experience-Oriented Power Adaptation for Smartphone`s Application Processor, In the Proceedings of IEEE/ACM Desing, Automation and Test in Europe (DATE) , 2013, 通讯作者
(29) AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture, In the Proceedings of High-Performance Computer Architecture Symposium 2012 (HPCA-18), 2012, 第 1 作者
(30) ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation, IEEE Transactions on Computers (TC), 2011, 第 1 作者
(31) SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation, IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), 2011, 第 1 作者
(32) MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2011, 第 1 作者
(33) Online Timing Variation Tolerance for Digital Integrated Circuits, In the Proceedings of International Test Conference (ITC), 2011, 第 1 作者
(34) Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors, In the Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA), 2010, 第 1 作者
(35) MicroFix: Exploiting Path-grained Timing Adaptability for Improving Power-Performance Efficiency, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2009, 第 1 作者
(36) A Unified Online Fault Detection Scheme via Checking of Stability Violation, IEEE/ACM Desing, Automation and Test in Europe (DATE), 2009, 第 1 作者
发表著作
(1) 数字集成电路容错设计--容缺陷/故障、容参数偏差、容软错误, Fault Tolerance Designs for Digital Integrated Circuits: Tolerating defects/faults, parameter variations, and soft errors, 科学出版社, 2010-04, 第 4 作者

科研活动

   
科研项目
( 1 ) 异构众核处理器功耗分析和管理优化, 主持, 国家级, 2012-01--2014-12
( 2 ) 高通量计算系统的构建原理、支撑技术及云服务应用, 参与, 国家级, 2011-01--2015-08
( 3 ) 大规模异构计算系统高时效协同功耗管理方法研究, 主持, 国家级, 2016-01--2019-12
( 4 ) 软件定义专用计算体系结构设计方法研究, 主持, 国家级, 2019-01--2022-12
( 5 ) 软件定义计算流图专用处理器体系结构研究, 主持, 市地级, 2019-01--2020-12
( 6 ) 中科驭数金融科技专用芯片与系统, 主持, 部委级, 2019-01--2019-12