Zunsong Yang received the B.E. degree in microelectronics from Qingdao University, Qingdao, China, in 2014, the M.E. degree in electronics and communications engineering from the University of Chinese Academy of Sciences (UCAS), Beijing, China, in 2017, and the Ph.D. degree in electrical and computer engineering from the University of Macau, Macao, China, in 2021. From 2021 to 2023, he was a Project Researcher with The University of Tokyo, Tokyo, Japan, where he worked on the design of low-jitter RF/mmW PLLs. Since 2023, he has been a Professor with the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), Beijing, China. 

His current research interests include frequency synthesizers, RF and mixed-signal integrated circuits for communications and radars. 

Dr. Yang was a recipient of the Akrostar Academic Prize from the University of Macau in 2021 and served as a Session Chair for IEEE ISCAS in 2024. He is currently serving as an Associate Editor for IEEE Solid-State Circuits Letters and Reviewer for the IEEE Journal of Solid-State Circuits, IEEE Solid-State Circuits Letters, IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE Transactions on Microwave Theory and Techniques, and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Google Scholar: https://scholar.google.com/citations?user=18p-4eQAAAAJ&hl=en&oi=ao

IEEE Xplore: https://ieeexplore.ieee.org/author/37086703326

   

[1] "Analog Integrated Circuit Analysis and Design", Postgraduates, School of Integrated Circuits, UCAS
[2] "Advanced Integrated Circuit Design and EDA", Postgraduates, School of Advanced Interdisciplinary Sciences, UCAS

   

[21] Tianle Chen=, Ruocun Wang=, Xiaoyu Shan*, Hongyu Ren*, Kai Cheng, Xuan Guo, Yunbo Huang, Li Wang, Zunsong Yang*, Bo Li, "Stability Analysis of Type-II Sampling and Subsampling Phase-Locked Loops," Microelectronics Journal (MEJ), vol. 175, Sept. 2026.

[20] Ruixi Yu, Qiyuan Liu, Li Wang*, Zunsong Yang*, et al., "A Compact 3 ~ 13-GHz Injection-Locked-and-PI Based Quadrature Clock Generator with 28.9-fs Jitter and 1120 μm2 Core Area," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. xx, no. xx, pp. xxx-xxx, xxx 2026.

[19] Yunbo Huang*, Zunsong Yang*, et al., "A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase Detector Achieving 53.8fsrms Jitter and −281.1dB FoMN," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. xx-xx, June 2026.

[18] Yunbo Huang, Zunsong Yang*, et al., "A 7.0-to-8.6GHz Balanced Class-F-1 VCO with a Trifilar Transformer-Based Tank Achieving 194.5dBc/Hz FoM," IEEE MTT-S Radio Frequency Integrated Circuits (RFIC), pp. xx-xx, June 2026.

[17]Rui Han, Li Wang*, Zunsong Yang*, et al., "A D-Band Power Amplifier with A Novel Gain Boosting Structure Achieving 15.8-dB Gain and 23.9-GHz Bandwidth in 65-nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, pp. xxx-xxx, May 2026.

[16]Bin Kong, Kai Cheng*, Hongyu Ren*, Xianghe Meng*, Xiaoyu Shan, Yunbo Huang, Li Wang, Zunsong Yang*, Bo Li, "2-GHz 5.06-mW Phase Accumulator Employing Dynamic Regulation for High-Speed Direct Digital Frequency Synthesizers in 65-nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, pp. xxx-xxx, May 2026.

[15] Ruixi Yu, Yunbo Huang*, Li Wang, Hongyu Ren, Xiaoyu Shan, Kai Cheng*, Zunsong Yang*, Bo Li, "A 0.3-V Compact VCO With Tail Filtering Using Double-8-Shaped Inductors in 65-nm CMOS," IEEE Microwave and Wireless Technology Letters (MWTL), vol. xx, no. xx, pp. xxx-xxx, xxx 2026.

[14] Kai Cheng, Yunbo Huang*, Zunsong Yang*, et al., "A 65nm 0.066pJ/bit Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 442-444, Feb. 2026.

[13] Yanzhe Kang, Hongyu Ren*, Zunsong Yang*, et al., "A 6.6-GHz Dual-Path Reference-Sampling PLL With 139.6-fs RMS Jitter and −75.2-dBc Spur in 28-nm CMOS," IET Electronics Letters (EL), vol. 61, Issue. 1, May 2025. 

[12] Hongyu Ren, Yunbo Huang*, Zunsong Yang*, et al., "A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, −91.9-dBc Reference Spur and −259-dB Jitter-Power FOM," IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, Sep. 2024. 

[11] Tianle Chen=, Hongyu Ren=, Zunsong Yang*, et al., "A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2024.

[10] Hongyu Ren, Zunsong Yang*, et al., "A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM,"  IEEE Microwave and Wireless Technology Letters (MWTL), vol. 34, no. 5, pp. 548-551, May 2024.

[9] Yuyang Zhu*, Zunsong Yang*, et al., "Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis," IEICE Transactions on Fundamentals, vol. E107-A, no. 5, pp. 746-750, May 2024.

[8] Zunsong Yang*, et al., "A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load," IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 2023.

[7] Zunsong Yang*, et al., "A 10-GHz Inductorless Cascaded PLL with Zero-ISF Sub-Sampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter And −240-dB FOMjitter," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2022.

[6] Zunsong Yang, et al., "A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 30, no. 2, pp. 238-242, Feb. 2022.

[5] Zunsong Yang, et al., "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 6, pp. 2307-2316, June 2021.

[4] Zunsong Yang, et al., "A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM," IEEE Solid-State Circuits Letters (SSCL), vol. 3, pp. 494-497, Oct. 2020.

[3] Zunsong Yang, et al., "A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector," IEEE Access, vol. 8, pp. 2222-2232, Dec. 2019.

[2] Zunsong Yang, et al., "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, pp. 283-284, Nov. 2019.

[1] Zunsong Yang, et al., "A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving −252.9dB Jitter-Power FoM And −63dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 270-272, Feb. 2019.

[1] Hao Guo, Zunsong Yang, Chee Cheow Lim, Harikrishnan Ramiah, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak & Rui P. Martins, Power-Efficient RF and mm-Wave VCOs/PLL, in Mixed-Signal Circuits in Nanoscale CMOS, Analog Circuits and Signal Processing, Springer, 2023.