面向高速有线/无线通信与高精度雷达感知，开展数模混合、射频、毫米波及亚太赫兹集成电路与系统设计研究。

每年计划招收博士研究生1～2名、硕士研究生1～2名。

招生专业

140100-集成电路科学与工程

080903-微电子学与固体电子学

招生方向

硅基振荡器、倍频器及频率综合器等信号源集成电路设计

硅基功率放大器与低噪声放大器等射频前端集成电路设计

射频、毫米波与亚太赫兹相控阵及收发机集成电路与系统设计

高速有线互联接口时钟产生、恢复与数据收发集成电路设计

学习经历

2017.08~2021.06：澳门大学（University of Macau），博士

2014.09~2017.07：中国科学院大学，中国科学院微电子研究所，硕士

2010.09~2014.07：青岛大学，本科

工作经历

2023.06~现在： 中国科学院微电子研究所, 研究员, 课题组长

2023.04~2023.06：中国科学院微电子研究所, 副研究员, 课题组长

2021.07~2023.03：日本东京大学（The University of Tokyo）, 特任研究员

学术兼职

IEEE Solid-State Circuits Letters 期刊副主编

IEEE ISCAS 2024 国际会议分会主席

教授课程

高等集成电路设计与EDA，研究生，学科核心课，首席教授，前沿交叉科学学院，中国科学院大学

模拟集成电路分析与设计，研究生，专业核心课，主讲教师，集成电路学院，中国科学院大学

代表性论文

IEEE Xplore: https://ieeexplore.ieee.org/author/37086703326

Google Scholar: https://scholar.google.com/citations?user=18p-4eQAAAAJ&hl=en&oi=ao

[21] Tianle Chen=, Ruocun Wang=, Xiaoyu Shan*, Hongyu Ren*, Kai Cheng, Xuan Guo, Yunbo Huang, Li Wang, Zunsong Yang*, Bo Li, "Stability Analysis of Type-II Sampling and Subsampling Phase-Locked Loops," Microelectronics Journal (MEJ), vol. 175, Sept. 2026.

[20] Ruixi Yu, Qiyuan Liu, Li Wang*, Zunsong Yang*, et al., "A Compact 3 ~ 13-GHz Injection-Locked-and-PI Based Quadrature Clock Generator with 28.9-fs Jitter and 1120 μm2 Core Area," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. xx, no. xx, pp. xxx-xxx, xxx 2026.

[19] Yunbo Huang*, Zunsong Yang*, et al., "A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase Detector Achieving 53.8fsrms Jitter and −281.1dB FoMN," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. xx-xx, June 2026.

[18] Yunbo Huang, Zunsong Yang*, et al., "A 7.0-to-8.6GHz Balanced Class-F-1 VCO with a Trifilar Transformer-Based Tank Achieving 194.5dBc/Hz FoM," IEEE MTT-S Radio Frequency Integrated Circuits (RFIC), pp. xx-xx, June 2026.

[17]Rui Han, Li Wang*, Zunsong Yang*, et al., "A D-Band Power Amplifier with A Novel Gain Boosting Structure Achieving 15.8-dB Gain and 23.9-GHz Bandwidth in 65-nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, pp. xxx-xxx, May 2026.

[16]Bin Kong, Kai Cheng*, Hongyu Ren*, Xianghe Meng*, Xiaoyu Shan, Yunbo Huang, Li Wang, Zunsong Yang*, Bo Li, "2-GHz 5.06-mW Phase Accumulator Employing Dynamic Regulation for High-Speed Direct Digital Frequency Synthesizers in 65-nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, pp. xxx-xxx, May 2026.

[15] Ruixi Yu, Yunbo Huang*, Li Wang, Hongyu Ren, Xiaoyu Shan, Kai Cheng*, Zunsong Yang*, Bo Li, "A 0.3-V Compact VCO With Tail Filtering Using Double-8-Shaped Inductors in 65-nm CMOS," IEEE Microwave and Wireless Technology Letters (MWTL), vol. xx, no. xx, pp. xxx-xxx, xxx 2026.

[14] Kai Cheng, Yunbo Huang*, Zunsong Yang*, et al., "A 65nm 0.066pJ/bit Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 442-444, Feb. 2026.

[13] Yanzhe Kang, Hongyu Ren*, Zunsong Yang*, et al., "A 6.6-GHz Dual-Path Reference-Sampling PLL With 139.6-fs RMS Jitter and −75.2-dBc Spur in 28-nm CMOS," IET Electronics Letters (EL), vol. 61, Issue. 1, May 2025. 

[12] Hongyu Ren, Yunbo Huang*, Zunsong Yang*, et al., "A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, −91.9-dBc Reference Spur and −259-dB Jitter-Power FOM," IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, Sep. 2024. 

[11] Tianle Chen=, Hongyu Ren=, Zunsong Yang*, et al., "A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2024.

[10] Hongyu Ren, Zunsong Yang*, et al., "A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM,"  IEEE Microwave and Wireless Technology Letters (MWTL), vol. 34, no. 5, pp. 548-551, May 2024.

[9] Yuyang Zhu*, Zunsong Yang*, et al., "Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis," IEICE Transactions on Fundamentals, vol. E107-A, no. 5, pp. 746-750, May 2024.

[8] Zunsong Yang*, et al., "A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load," IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 2023.

[7] Zunsong Yang*, et al., "A 10-GHz Inductorless Cascaded PLL with Zero-ISF Sub-Sampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter And −240-dB FOMjitter," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2022.

[6] Zunsong Yang, et al., "A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 30, no. 2, pp. 238-242, Feb. 2022.

[5] Zunsong Yang, et al., "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 6, pp. 2307-2316, June 2021.

[4] Zunsong Yang, et al., "A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM," IEEE Solid-State Circuits Letters (SSCL), vol. 3, pp. 494-497, Oct. 2020.

[3] Zunsong Yang, et al., "A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector," IEEE Access, vol. 8, pp. 2222-2232, Dec. 2019.

[2] Zunsong Yang, et al., "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, pp. 283-284, Nov. 2019.

[1] Zunsong Yang, et al., "A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving −252.9dB Jitter-Power FoM And −63dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 270-272, Feb. 2019.

代表性书籍/章节

[1] Hao Guo, Zunsong Yang, Chee Cheow Lim, Harikrishnan Ramiah, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak & Rui P. Martins, Power-Efficient RF and mm-Wave VCOs/PLL, in Mixed-Signal Circuits in Nanoscale CMOS, Analog Circuits and Signal Processing, Springer, 2023.

国家自然科学基金面上项目，50万，负责人，2026.01~2029.12

中国科学院项目，800万（含所匹配），负责人，2025.01~2026.12

国家青年人才项目，500万（含院匹配），负责人，2024.01~2026.12

研究所前瞻研究计划人才团队项目，400万，负责人，2023.01~2025.12

博士研究生

陈天乐，2021.09 ~

于照汐，2021.09 ~

刘石，2022.09 ~

吴铭，2024.09 ~

王若存，2024.09 ~

刘益男，2025.09 ~

周昱，2025.09 ~

杨昊，2026.09 ~

硕士研究生

王诗睿，2024.09 ~

尹成展，2024.09 ~

徐梓鑫，2024.09 ~

陈禹良，2024.09 ~

韩嘉毅，2024.09 ~

蔡晓阳，2025.09 ~

李嘉源，2025.09 ~

单柳玥，2026.09 ~

吴屿桐，2026.09 ~

​博士毕业生及去向

任洪宇，2019.09 ~ 2024.07，留所任职助理研究员/特别研究助理/博士后，中国科学院微电子研究所

余蕊汐，2021.09 ~ 2026.07，模拟IC设计工程师，振芯科技

硕士毕业生及去向

俸超平，2021.09 ~ 2024.07，读博深造，南方科技大学 

张心铭，2021.09 ~ 2024.07，射频IC设计工程师，海信

亢延哲，2022.09 ~ 2025.07，读博深造，香港科技大学（广州）

韩瑞，2023.09 ~ 2026.07，射频IC设计工程师，北京昂润微

孔斌，2023.09 ~ 2026.07，ASIC设计工程师，上海兆芯

陈威廷，2023.09 ~ 2026.07，模拟IC设计工程师，杭州艾诺半导体