主要从事面向5G/6G、高速接口等新一代通信系统的高性能频率综合器和收发机芯片研究工作

课题组每年计划招生1~2名博士，2~3名硕士

140100-集成电路科学与工程
080903-微电子学与固体电子学

模拟、混合信号、射频集成电路设计
硅基压控振荡器、频率综合器、收发机芯片设计
硅基功率放大器、低噪声放大器等射频前端电路设计

2023.06~现在： 中国科学院微电子研究所, 研究员, 课题组长
2023.04~2023.06：中国科学院微电子研究所, 副研究员, 课题组长
2021.07~2023.03：日本东京大学（The University of Tokyo）, 特任研究员
2017.08~2021.06：澳门大学（University of Macau），博士研究生

[1] IEEE Solid-State Circuits Letters 期刊副主编
[2] IEEE ISCAS 2024国际会议分会主席
[3] IEEE Journal of Solid-State Circuits 期刊审稿人
[4] IEEE Solid-State Circuits Letters 期刊审稿人
[5] IEEE Transactions on Circuits and Systems I: Regular Papers 期刊审稿人
[6] IEEE Transactions on Microwave Theory and Techniques 期刊审稿人

   

高等集成电路设计与EDA

   

IEEE Xplore: https://ieeexplore.ieee.org/author/37086703326

Google Scholar: https://scholar.google.com/citations?user=18p-4eQAAAAJ&hl=en&oi=ao

[17] Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui P. Martins, Yan Lu, Nan Sun, Nan Qi, and Yong Chen, "A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and −254.3dB FoM," IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, April 2025. (Accepted)

[16] Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment," IEEE Journal of Solid-State Circuits (JSSC), 2024. (Accepted)

[15] Hua Xu, Xuqiang Zheng, Zedong Wang, Yu He, Fangxu Lv, Mingche Lai, Zunsong Yang, Xuan Guo, Zhi Jin, Xinyu Liu, "A 112Gb/s PAM4 Retimer Transceiver with Jitter-Filtering Clocking Scheme and BER Optimization Scoring 252fsrms Clock Jitter and 10-12 BER," IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, Sep. 2024. 

[14] Hongyu Ren, Yunbo Huang*, Zunsong Yang*, Tianle Chen, Xianghe Meng, Weiwei Yan, Weidong Zhang, Zhongmao Li, Tetsuya Iizuka, Pui-In Mak, Yong Chen and Bo Li*, "A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, −91.9-dBc Reference Spur and −259-dB Jitter-Power FOM," IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, Sep. 2024. 

[13] Hongyu Ren, Zunsong Yang*, Yunbo Huang, Chaoping Feng, Tianle Chen, Xinming Zhang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Tetsuya Iizuka, Yong Chen, Pui-In Mak, Zhengsheng Han*, Bo Li*, "A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM,"  IEEE Microwave and Wireless Technology Letters (MWTL), vol. 34, no. 5, pp. 548-551, May 2024.

[12] Tianle Chen=, Hongyu Ren=, Zunsong Yang*, Yunbo Huang*, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, and Bo Li*, "A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2024.

[11] Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka, "A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division with Phase-Domain Filtering," IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 7, pp. 2171-2184, July 2024.

[10] Yu He, Xuqiang Zheng, Zedong Wang, Zunsong Yang, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu, "An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9 fs RMS Jitter and-255.5 dB FoM", IEEE Custom Integrated Circuits Conference (CICC), Denver, CO, USA, April 2024

[9] Yunbo Huang, Yong Chen, Zunsong Yang, Rui P. Martins, Pui-In Mak, "A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.

[8] Zunsong Yang*, Masaru Osada, Shuowei Li, Yuyang Zhu, and Tetsuya Iizuka, "A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load," IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 2023.

[7] Zunsong Yang*, Zule Xu, Masaru Osada and Tetsuya Iizuka, "A 10-GHz Inductorless Cascaded PLL with Zero-ISF Sub-Sampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter And −240-dB FOMjitter," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2022.

[6] Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak and Rui P. Martins, "A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving −252.9dB Jitter-Power FoM And −63dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 270-272, Feb. 2019.

[5] Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, pp. 283-284, Nov. 2019.

[4] Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 6, pp. 2307-2316, June 2021.

[3] Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM," IEEE Solid-State Circuits Letters (SSCL), vol. 3, pp. 494-497, Oct. 2020.

[2] Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak and Rui P. Martins, "A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 30, no. 2, pp. 238-242, Feb. 2022.

[1] Yong Chen, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, Pui-In Mak and Rui P. Martins, "A 6.5×7μm2 0.98-to-1.5mW Non-Self-Oscillation-Mode Frequency Divider-By-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)," IEEE Solid-State Circuits Letters (SSCL), vol. 2, no. 5, pp. 37-40, May 2019.

[1] Hao Guo, Zunsong Yang, Chee Cheow Lim, Harikrishnan Ramiah, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak & Rui P. Martins, Power-Efficient RF and mm-Wave VCOs/PLL, in Mixed-Signal Circuits in Nanoscale CMOS, Analog Circuits and Signal Processing, Springer, 2023.

国家级高层次青年人才项目，国家级，负责人, 2024.01~2026.12
中国科学院高层次青年人才项目，部委级，负责人, 2024.01~2026.12
研究所自主部署前瞻研究计划团队项目，市地级，负责人, 2023.01~2025.12

副研究员：闫薇薇，张卫东

高级工程师：孟祥鹤

助理研究员/博士后/特别研究助理：任洪宇，成凯

陈天乐，2021.09 ~
余蕊汐，2021.09 ~
于照汐，2021.09 ~
刘   石，2022.09 ~
吴   铭，2024.09 ~
王若存，2024.09 ~
张建喜，2024.09 ~

亢延哲，2022.09 ~
韩   瑞，2023.09 ~
孔   斌，2023.09 ~
王钦旭，2023.09 ~
王诗睿，2024.09 ~
尹成展，2024.09 ~
徐梓鑫，2024.09 ~
么禹城，2024.09 ~
陈禹良，2024.09 ~
韩嘉毅，2024.09 ~

​

任洪宇，2019.09 ~ 2024.07，留所任职助理研究员/特别研究助理/博士后，中国科学院微电子研究所

俸超平，2021.09 ~ 2024.07，读博深造，南方科技大学 
张心铭，2021.09 ~ 2024.07，射频电路工程师，海信