I work at the Intelligent Computing Research Center, Institute of Computing Technology, Chinese Academy of Sciences.My research focuses on 2.5D/3D processor design and EDA.

Previous Research Directions:

1. Processor Chip Design (Engineering):

• Processor architecture design and SoC design.
• Served as the primary technical lead for designing chips such as Dadu-B, Dadu 2.0, and Zhejiang Big Chip No. 1.
• Led project teams to execute architecture, RTL, packaging scheme, system board scheme, and chassis architecture design.
• Deliverables from this work fulfilled requirements for major national science and technology project evaluations.

1. EDA for 2.5D/3D Split Manufacturing & Chiplet Design:

• Placement and routing (P&R) tools specifically designed for 2.5D/3D scenarios.
• The tools address design metrics such as security and timing during split design.

Current Research Directions:

1. Advanced packaging substrate design (focusing on interconnect structures).
2. Physical design EDA for large-scale substrates (placement, routing, power delivery).
3. Architecture-packaging co-design for 2.5D/3.5D processors (System-Technology Co-Optimization, STCO).

• N for One: Reticle-Reuse-Driven Routing for Silicon Interposers, X Lin, Y Wang*, L Feng, J Zhu, X Lu, Y Wang, F Dai, Y Han. GLSVLSI '26: Proceedings of the Great Lakes Symposium on VLSI 2026. Proceedings of the Great Lakes Symposium on VLSI 2026 (GLSVLSI '26), 2026
• Chiplet Design Automation: Methodologies, Advances, and Directions, F Li, D Yuan, J Zhu, X Liang, J Zhou, T Miao, H Li, K Zhang, Y Han, H Li, X Li, Y Wang*, and Y Wang*. ACM Transactions on Design Automation of Electronic Systems (TOADES), 2026
• Chipletizer 2.0: Towards Cost-Effective Chiplet Design via Reuse-Aware Decomposition，F Li, D Yuan. Y Wang*, J Zhou, X Liang, Y Han,  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025
• Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks， X Wang, L Feng, Y Wang*, T Xu, Y Han, Z Wang, ACM Transactions on Design Automation of Electronic Systems (TOADES), 2025
• CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC，X Liang, Y Wang*, X Lu, L Feng, J Zhu, Y Wang, Y Han, 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025
• Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration，F Li, Y Wang, Y Wang, M Wang, Y Han, H Li, X Li, 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 58-64 2024
• Gia: A reusable general interposer architecture for agile chiplet integration,F Li, Y Wang, Y Cheng, Y Wang, Y Han, H Li, X Li, Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided (ICCAD),2022
• Survey on chiplets: interface, interconnect and integration methodology, X Ma, Y Wang, Y Wang, X Cai, Y Han, CCF Transactions on High Performance Computing 4 (1), 43-52 20 2022
• Dadu-eye: A 5.3 TOPS/W, 30 fps/1080p high accuracy stereo vision accelerator, F Min, H Xu, Y Wang, Y Wang, J Li, X Zou, B Li, Y Han, IEEE Transactions on Circuits and Systems I: Regular Papers 68 (10), 4207-4220 11 2021
• Making split fabrication synergistically secure and manufacturable, L Feng, Y Wang, J Hu, WK Mak, J Rajendran, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 313-320 13 2017
• Front-end-of-line attacks in split manufacturing, Y Wang, T Cao, J Hu, J Rajendran, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8 14 2017
• Routing perturbation for enhanced security in split manufacturing, Y Wang, P Chen, J Hu, JJV Rajendran, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 605-510 40 2017
• The cat and mouse in split manufacturing, Y Wang, P Chen, J Hu, J Rajendran, Proceedings of the 53rd Annual Design Automation Conference, 1-6