General

Dr Jiangwei Zhang

Associate Professor
Institute of Information Engineering, Chinese Academy of Sciences
Email: zhangjiangwei@iie.ac.cn
Address: No. 19 Shucun Road, Haidian District, Beijing, China

Research Areas

Dr Zhang's research focuses on large model inference acceleration, memory reliability, and privacy-preserving inference. He has published a few papers as the first author or corresponding author in the field of computer architecture, including several in CCF-A top-tier conferences and journals such as HPCA, DAC, and IEEE TC. He has also published in other prestigious conferences and journals, including ICCAD, IEEE TVLSI, ICCD, ISVLSI, and IEEE CAL. 

Education

2016.10 – 2018.10 University of Pittsburgh, USA Visiting Ph.D. Student
2015.03 – 2018.12 National University of Defense Technology Ph.D.
2012.09 – 2014.12 National University of Defense Technology M.S.
2008.09 – 2012.06 National University of Defense Technology B.S.

Experience

   
Work Experience

2024.01 – Present Institute of Information Engineering, Chinese Academy of Sciences, National Key Laboratory of Cyberspace Security Defense Associate Professor

2021 – 2023 Department of Electronic Engineering, Tsinghua University Assistant Researcher (Postdoctoral Researcher)

Publications

   
Papers

​[IEEE TC'25] C. Wang, W. Fu, J. Zhang*, S. Li, R. Hou, J. Yang, Y. Wang, “WOLF: Weight-Level OutLier and Fault Integration for Reliable LLM Deployment”, IEEE Transactions on Computers, accepted. (CCF-A)

[DAC'23] S. Li, Z. Zhu, Y. Zhu, Q. Zhu, J. Zhang*, W. Sun, G. Dai, F. Qiao, H. Yang and Y.Wang*,“Memory-Efficient and Real-Time SPAD-based dToF Imaging with Spatial and Statistical Correlation”, Design Automation Conference (DAC) 2023. (CCF-A)

[HPCA'23] J. Zhang*, C. Wang, Z. Zhu, D. Kline Jr, A. Jones, H. Yang, Y. Wang*, “Realizing Extreme Endurance Through Fault-aware Wear Leveling and Improved Tolerance”, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023. (CCF-A)

[ISVLSI'22] J. Zhang*, C. Wang, Y. Cai, Z. Zhu, D. Kline Jr, H. Yang, Y. Wang*, “WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022.

[HPCA'20] D. Kline Jr*, J. Zhang*, R. G. Melhem*, and A. K. Jones*, “FLOWER and FaME: A Low Overhead Bit-level Fault-map and Fault-tolerance Approach for Deeply Scaled Memories,” IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2020. (CCF-A)

[IEEE CALs'18]  J. Zhang, D. Kline Jr, L. Fang, R. G. Melhem, and A. K. Jones, “RETROFIT: Fault-aware Wear Leveling,” IEEE Computer Architecture Letters, 2018.

[IEEE TVLSI'18] J. Zhang, D. Kline Jr, L. Fang, R. G. Melhem, and A. K. Jones, Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories. IEEE Transactions on VLSI Systems  (2018): 1-14. 

[ICCD'17] J. Zhang, D. Kline, L. Fang, R. Melhem, and A. K. Jones, “Yoda: Judge me by my size, do you?,” IEEE International Conference on Computer Design (ICCD), pp. 395–398, IEEE, 2017.

[ICCAD'17] J. Zhang, D. Kline Jr, L. Fang, R. Melhem, and A. K. Jones, “Dynamic partitioning to mitigate stuck-at faults in emerging memories,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 651–658, IEEE, 2017.