Novel Semicondutor Devices

Integrated Circuit Advanced Process

HfO2-based Ferroelectric Materials and Devices

Thin Film Transistor and 3D Integration

Advanced Semiconductor Detector

Ph.D.

   

2021-07~Now, Institute of Microelectronics of Chinese Academy of Sciences, Professor

2011-09~2021-07, Institute of Microelectronics of Chinese Academy of Sciences, Associate Professor

2009-07~2011-09, Institute of Microelectronics of Chinese Academy of Sciences, Assistant Professor

2016-11~2017-12, The University of Texas at Austin, Visiting Scholar

2003-09~2009-07, Institute of Microelectronics of Chinese Academy of Sciences, Ph.D.

1998-09~2002-07, Shandong University, B.S.

   

（1） Single-event-transient effects in silicon-on-insulator ferroelectric double-gate vertical tunneling field effect transistors, Science China Information Sciences, 2020, 通讯作者
（2） Heavy ion induced single-event-transient effects in nanoscale ferroelectric vertical tunneling transistors by TCAD simulation, Semiconductor Science and Technology, 2020, 通讯作者
（3） Accumulative total ionizing dose (TID) and transient dose rate (TDR) effects on planar and vertical ferroelectric tunneling-field-effect-transistors (TFET), Microelectronics Reliability, 2020, 通讯作者
（4） Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor, IEEE Access, 2020, 通讯作者
（5） Total Ionization Dose Effects of N-type Tunnel Field Effect Transistor (TFET) with Ultra-Shallow Pocket Junction, Applied Physics A, 2020, 通讯作者
（6） Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process, Materials Science in Semiconductor Processing, 2020, 其他（合作组作者）
（7） 一种硅漂移探测器的优化设计与特性研究, 传感技术学报, 2020, 第 4 作者
（8） Fabrication and characterization of a novel Si line tunneling TFET with high drive current, IEEE Journal of the Electron Devices Society, 2020, 通讯作者
（9） Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device, Journal of Materials Science Materials in Electronics, 2020, 第 10 作者
（10） Hf0.5Zr0.5O2-based ferroelectric bionic electronic synapse device with highly symmetrical and linearity weight modification, Electronics Letters, 2020, 第 3 作者
（11） High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer, Materials Science in Semiconductor Processing, 2019, 第 8 作者
（12） FinFET with Improved Subthreshold Swing and Drain Current using 3 nm Ferroelectric Hf0.5Zr0.5O2, IEEE Electron Device Letters, 2019, 第 2 作者
（13） Process Optimization of the Si0.7Ge0.3 Fin Formation for the STI First Scheme, Semiconductor Science and Technology, 2019, 第 7 作者
（14） Internal Filament Modulation in Low-dielectric Gap Design for Built-in Selector-less Resistive Switching Memory Application, Journal of Physics D: Applied Physics, 2018, 第 8 作者
（15） Study of γ-ray irradiation influence on TiN/HfO2 /Si MOS capacitor by C-V and DLTS, Superlattices and Microstructures, 2018, 第 10 作者
（16） 隧穿场效应晶体管的研究进展, 微纳电子技术, 2018, 通讯作者
（17） Total Ionization Dose Effects on Charge Storage Capability of Al2O3/HfO2/Al2O3 (AHA)-based Charge Trapping Memory (CTM) Cell, Chinese Physics Letters, 2018, 第 3 作者
（18） Band-Edge Work Function Obtained by Plasma Doping TiN Metal Gate for nMOS Device Application, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 第 3 作者
（19） Beyond SiOx: An Active Electronics Resurgence and Biomimetic Reactive Oxygen Species Production and Regulation from Mitochondrion, Journal of Materials Chemistry C, 2018, 第 5 作者
（20） 硅基Ⅲ-Ⅴ族纳米线及其若干半导体器件, 半导体技术, 2017, 通讯作者
（21） Total ionizing dose effects and annealing behaviors of HfO2 based MOS capacitor, Science China Information Science, 2017, 第 3 作者
（22） Total Ionization Dose Effects on Charge Trapping Memory (CTM) with Al2O3/HfO2/Al2O3 Trilayer Structure, IEEE Transactions on Nuclear Science, 2017, 第 3 作者
（23） Attainment of Dual-band Edge Work Function by Using a Single Metal Gate and Single High-k Dielectric Via Ion Implantation for HP CMOS Device, Solid-State Electronics, 2016, 第 2 作者
（24） Ion Implanted TiN Metal Gate With Dual-band Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications, IEEE Transactions on Electron Devices, 2015, 第 2 作者
（25） Investigation of Key Technologies for Poly-Si/TaN/fLaON/IL SiO2 Gate-Stacks in Advanced Device Applications, IEEE Transactions on Electron Devices, 2014, 第 2 作者
（26） Study of Si Green Transistor with an Ultra-shallow Pocket Junction, ECS Transactions, 2014, 第 1 作者
（27） Characteristics of HfLaON/SiO2 Gate Stack prepared using Reactive Sputtering, ECS Transactions, 2013, 第 1 作者
（28） Characterization of HfSiAlON/MoAlN PMOSFET Fabricated by Using a Novel Gate-Last Process, Chinese Physics Letters, 2013, 第 1 作者
（29） A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process, Chinese Physics B, 2013, 第 1 作者
（30） CMP-Less Planarization Technology with SOG/LTO Etchback for Low-Cost High-k/Metal Gate-Last Integration, ECS Journal of Solid State Science and Technology, 2013, 第 4 作者
（31） HfSiON High-k Layer Compatibility Study with TetraMethyl Ammonium Hydroxide (TMAH) Solution, Electrochemical and Solid-State Letters, 2012, 第 3 作者
（32） CMP-less Planarization Technology with SOG/LTO Etchback for Low Cost 70nm Gate-Last Process, ECS Transactions, 2011, 第 4 作者
（33） Gallium-incorporated TiN metal gate with band-edge work function and excellent thermal stability for PMOS device applications, IEEE Electron Device Letters, 2011, 第 2 作者
（34） Characteristics of HfSiAlON Gate Dielectric Prepared by Physical Vapor Deposition, ECS Transactions, 2011, 第 1 作者

（1） Improved Electrical Characteristics of P-type Tunnel Field-Effect Transistor With Source-Pocket Junction Formed Using High-Angle Implantation   2019-10-14
（2）A High-Performance Source-Pocket Tunnel Field-Effect Transistor   2019-03-18
（3）CMOS-compatible Hf0.5Zr0.5O2-based Ferroelectric Capacitors for Negative Capacitance and Non-volatile Applications   2018-10-31
（4）Study of a novel N-type Tunneling FET with a Si1-xGex/Si hetero-pocket   2017-12-06
（5）Built-in Nonlinear Characteristics of Low Power Operating One-Resistor Selector-Less RRAM By Stacking Engineering   2017-10-01
（6）Nonlinear Characteristics of Low Power Operating HfOx/SiOx Stacking Selectorless RRAM   2017-06-25
（7）FOI FinFET with Ultra-low Parasitic Resistance Enabled by Fully Metallic Source and Drain Formation on Isolated Bulk-Fin   2016-12-03
（8）SiGe Selective Epitaxial Growth Process for 22nm Node CMOS and Beyond   2014-05-14
（9）Study of Hetero-Tunneling gFET with an Ultra-Shallow Pocket Junction   2014-05-14
（10）Study of Si Green Transistor with an Ultra-shallow Pocket Junction    2014-03-16
（11）High-quality HfSiON gate dielectric and its application in a gate-last NMOSFET fabrication   2013-06-03
（12）Characteristics of HfLaON/SiO2 Gate Stack prepared using Reactive Sputtering   2013-03-17
（13）Characteristics of HfSiAlON Gate Dielectric Prepared by Physical Vapor Deposition   2011-03-13