半导体器件物理及建模

器件可靠性及建模

2017-09--2021-05   比利时天主教鲁汶大学(KU Leuven) &imec   博士
2013-10--2017-03   德国亚琛工业大学(RWTH)   硕士
2009-09--2013-06   北京航空航天大学   学士

   

2023-11~现在, 中国科学院微电子研究所, 研究员
2022-09~2023-10,中国科学院微电子研究所, 副研究员
2021-06~2022-08,比利时校际微电子研究中心(imec), 研究员

   

（1） Z. Wu, A. Chasin, J. Franco et al., "Characterizing and Modelling of the BTI Reliability in IGZO-TFT using Light-assisted I-V Spectroscopy,", 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 30.1.1-30.1.4, doi: 10.1109/IEDM45625.2022.10019454., 2022, 第 1 作者
（2） Z. Wu, J. Franco, A. Vandooren, H. Arimura et al., "LaSiOₓ- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration,", in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2022.3141983., 2022, 第 1 作者
（3） Z. Wu, J. Franco, B. Truijen et al., "Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET,", in IEEE Transactions on Electron Devices, vol. 68, no. 7, pp. 3246-3253, July 2021, doi: 10.1109/TED.2021.3080657., 2021, 第 1 作者
（4） Z. Wu, J. Franco, B. Truijen et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment,", 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106., 2021, 第 1 作者
（5） Z. Wu, J. Franco, A. Vandooren et al., "Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration,", in IEEE Transactions on Electron Devices, vol. 68, no. 2, pp. 464-470, Feb. 2021, doi: 10.1109/TED.2020.3041813., 2021, 第 1 作者
（6） A. Vandooren, Z. Wu, J. Franco et al., "3D sequential CMOS top tier devices demonstration using a low temperature Smart Cut™ Si layer transfer,", 2021 Silicon Nanoelectronics Workshop (SNW), 2021, pp. 1-2, doi: 10.1109/SNW51795.2021.00025., 2021, 第 2 作者
（7） A. Vandooren, Z. Wu, N. Parihar et al., "3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters,", 2020 IEEE Symposium on VLSI Technology, 2020, pp. 1-2, doi: 10.1109/VLSITechnology18217.2020.9265026., 2020, 第 2 作者
（8） A. Vandooren, Z. Wu, A. Khaled et al., "Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications,", 2019 Symposium on VLSI Technology, 2019, pp. T56-T57, doi: 10.23919/VLSIT.2019.8776490., 2019, 第 2 作者
（9） J. Franco, Z. Wu, G. Rzepa et al., "Low Thermal Budget Dual-Dipole Gate Stacks Engineered for Sufficient BTI Reliability in Novel Integration Schemes,", 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019, pp. 215-217, doi: 10.1109/EDTM.2019.8731237., 2019, 第 2 作者
（10） Z. Wu, J. Franco, P. J. Roussel et al., "A physics-aware compact modeling framework for transistor aging in the entire bias space,", 2019 IEEE International Electron Devices Meeting (IEDM), 2019, pp. 21.2.1-21.2.4, doi: 10.1109/IEDM19573.2019.8993603., 2019, 第 1 作者
（11） Z. Wu, J. Franco, D. Claes et al., "Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling,", 2019 IEEE International Reliability Physics Symposium (IRPS), 2019, pp. 1-7, doi: 10.1109/IRPS.2019.8720541., 2019, 第 1 作者
（12） Z. Wu, J. Franco, A. Vandooren et al., "Improved PBTI Reliability in Junction-Less FET Fabricated at Low Thermal Budget for 3-D Sequential Integration,", in IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 262-267, June 2019, doi: 10.1109/TDMR.2019.2906843., 2019, 第 1 作者
（13） J. Franco, Z. Wu et al., "On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI,", in IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 268-274, June 2019, doi: 10.1109/TDMR.2019.2913258., 2019, 第 2 作者
（14） J. Franco, Z. Wu, G. Rzepa et al., "On the Impact of the Gate Metal Work-Function on the Charge Trapping Component of BTI,", 2018 International Integrated Reliability Workshop (IIRW), 2018, pp. 1-4, doi: 10.1109/IIRW.2018.8727089., 2018, 第 2 作者
（15） J. Franco, Z. Wu, G. Rzepa et al., "BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration,", 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 34.2.1-34.2.4, doi: 10.1109/IEDM.2018.8614559., 2018, 第 2 作者
（16） Z. Wu, J. Franco, A. Vandooren et al., "Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration,", 2018 International Integrated Reliability Workshop (IIRW), 2018, pp. 1-4, doi: 10.1109/IIRW.2018.8727075., 2018, 第 1 作者

   

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