集成电路先导工艺技术

2001-10--2004-03   北京科技大学   硕士
1993-09--1997-07   曲阜师范大学   学士

   

2012-08~现在, 中国科学院微电子研究所, 高级工程师
2004-04~2012-08,中芯国际集成电路（北京）有限公司, 工程师
1997-08~2001-09,山东省新汶矿业集团公司第一中学, 教师

   

[1] 朱慧珑, 张永奎. 半导体器件及其制造方法及包括其的电子设备. CN: CN109473429B, 2021-08-03.
[2] 张青竹, 殷华湘, 曹磊, 张兆浩, 顾杰, 田佳佳, 李俊杰, 姚佳欣, 李永亮, 张永奎, 吴振华, 赵鸿滨, 罗军, 王文武, 屠海令, 叶甜春. 一种半导体器件的制备方法及半导体器件. CN: CN113178488A, 2021-07-27.
[3] 吴振华, 甘维卓, 张兆浩, 张永奎, 李俊杰, 殷华湘, 朱慧珑, 郭鸿. 一种半导体器件及其制造方法、集成电路、电子设备. CN: CN112652664A, 2021-04-13.
[4] 张青竹, 殷华湘, 闫江, 吴振华, 周章渝, 秦长亮, 张严波, 张永奎. 半导体器件及其制作方法. CN: CN107068769B, 2020-12-08.
[5] 朱慧珑, 艾学正, 张永奎. 具有交错结构的半导体装置及其制造方法及电子设备. CN: CN111584486A, 2020-08-25.
[6] 朱慧珑, 尹晓艮, 李晨, 都安彦, 张永奎. 一种高精度的刻蚀方法. CN: CN110867373A, 2020-03-06.
[7] 张永奎, 朱慧珑, 卢维尔, 夏洋, 李琳, 郭晓龙, 尹晓艮, 文庆涛. 一种刻蚀装置及刻蚀方法. CN: CN110581095A, 2019-12-17.
[8] 尹晓艮, 朱慧珑, 万光星, 张永奎. 一种垂直纳米线MOSFET及其制造方法. CN: CN106711227B, 2019-11-08.
[9] 甘维卓, 张永奎, 李俊杰, 吴振华, 郭鸿, 殷华湘, 朱慧珑, 王文武. 冷源结构MOS晶体管及其制作方法. CN: CN109920842A, 2019-06-21.
[10] 朱慧珑, 李晨, 张永奎. 半导体器件及其制造方法及包括该器件的电子设备. CN: CN109888001A, 2019-06-14.
[11] 殷华湘, 张永奎, 赵治国, 朱慧珑. 鳍式场效应晶体管的制造方法. CN: CN105513968B, 2019-03-08.
[12] 朱慧珑, 张永奎, 尹晓艮, 李晨, 刘永波, 贾昆鹏. 半导体器件及其制造方法及包括该器件的电子设备. 中国: CN109449121A, 2019-03-08.
[13] 朱慧珑, 黄伟兴, 张永奎, 尹晓艮, 李晨, 贾昆鹏. 半导体器件及其制造方法及包括该器件的电子设备. 中国: CN109449206A, 2019-03-08.
[14] 殷华湘, 张永奎, 赵治国, 陆智勇, 朱慧珑. 半导体器件及其制造方法. 中国: CN105489652B, 2018-09-18.
[15] 朱慧珑, 赵治国, 张永奎, 马小龙, 许淼, 殷华湘, 杨红. 半导体设置及其制造方法. 中国: CN104716171B, 2018-07-06.
[16] 徐强, 熊文娟, 张永奎, 殷华湘. 控制鳍式场效应晶体管器件鳍片尺寸的方法. 中国: CN105374682B, 2018-01-02.
[17] 张青竹, 殷华湘, 闫江, 吴振华, 周章渝, 秦长亮, 张严波, 张永奎. 半导体器件及其制作方法. 中国: CN107068769A, 2017-08-18.
[18] 张永奎, 殷华湘, 朱慧珑, 钟健. 一种形成小间距鳍体的方法. 中国: CN106601610A, 2017-04-26.
[19] Yin Huaxiang, 张永奎, Zhao Zhiguo, Lu Zhiyong, Zhu Huilong. Semiconductor device and method for manufacturing the same. 美国: US9431504(B2), 2016.08.30.
[20] 崔虎山, 熊文娟, 殷华湘, 罗军, 张永奎, 徐强, 朱慧珑, 赵超. 一种后栅工艺中ILD层的处理方法. 中国: CN104637797A, 2015-05-20.
[21] 殷华湘, 张永奎, 朱慧珑. 半导体器件及其制造方法. 中国: CN104112666A, 2014-10-22.

   

[1] Zhang, Zhaohao, Gan, Weizhuo, Li, Junjie, Kong, Zhenzhen, Han, Yanchu, Liu, Yang, Wang, Guilei, Wu, Zhenhua, Yu, Jiahan, Zhang, Qingzhu, Xu, Gaobo, Zhang, Yongkui, Xiang, Jinjuan, Yin, Huaxiang, Luo, Jun, Wang, Wenwu. Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current. MATERIALSSCIENCEINSEMICONDUCTORPROCESSING[J]. 2022, 140: http://dx.doi.org/10.1016/j.mssp.2021.106337.
[2] Huang, Weixing, Zhu, Huilong, Zhang, Yongkui, Yin, Xiaogen, Ai, Xuezheng, Li, Junjie, Li, Chen, Li, Yangyang, Xie, Lu, Liu, Yongbo, Xiang, Jinjuan, Jia, Kunpeng, Li, Junfeng, Ye, T C. Ferroelectric Vertical Gate-All-Around Field-Effect-Transistors With High Speed, High Density, and Large Memory Window. IEEE ELECTRON DEVICE LETTERS[J]. 2022, 43(1): 25-28, [3] Zhang, Zhaohao, Luo, Yanna, Cui, Yan, Yang, Hong, Zhang, Qingzhu, Xu, Gaobo, Wu, Zhenhua, Xiang, Jinjuan, Liu, Qianqian, Yin, Huaxiang, Mao, Shujuan, Wang, Xiaolei, Li, Junjie, Zhang, Yongkui, Luo, Qing, 高建峰, Xiong, Wenjuan, Liu, Jinbiao, Li, Yongliang, Li, Junfeng, Luo, Jun, Wang, Wenwu. A Polarization-Switching, Charge-Trapping, Modulated Arithmetic Logic Unit for In-Memory Computing Based on Ferroelectric Fin Field-Effect Transistors. ACS APPLIED MATERIALS & INTERFACES[J]. 2022, 14(5): 6967-6976, http://dx.doi.org/10.1021/acsami.1c20189.
[4] Yongbo Liu, Huilong Zhu, Yongkui Zhang, Xiaolei Wang, Weixing Huang, Chen Li, Xuezheng Ai, Qi Wang. Vertical nanowire/nanosheet FETs with a horizontal channel for threshold voltage modulation. 半导体学报:英文版[J]. 2022, 43(1): 81-89, http://lib.cqvip.com/Qikan/Article/Detail?id=7106536572.
[5] Huang, Weixing, Zhu, Huilong, Zhang, Yongkui, Wu, Zhenhua, Huo, Qiang, Xiao, Zhongrui, Jia, Kunpeng. Ternary Logic Circuit Based on Negative Capacitance Field-Effect Transistors and Its Variation Immunity. IEEETRANSACTIONSONELECTRONDEVICES[J]. 2021, 68(7): 3678-3683, http://dx.doi.org/10.1109/TED.2021.3081523.
[6] Huang, Weixing, Zhu, Huilong, Zhang, Yongkui, Wu, Zhenhua, Jia, Kunpeng, Yin, Xiaogen, Li, Yangyang, Li, Chen, Ai, Xuezheng, Huo, Qiang, Li, Junfeng. Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits. MICROELECTRONICS JOURNAL[J]. 2021, 114: http://dx.doi.org/10.1016/j.mejo.2021.105110.
[7] Chen Li, 朱慧珑, 张永奎. First Demonstration of Novel Vertical Gate-All-Around Field-Effect- Transistors Featured by Self-Aligned and Replaced High‑κ Metal Gates. ACS,Nano letters[J]. 2021, [8] Huang, Weixing, Zhu, Huilong, Zhang, Yongkui, Xiang, Jinjuan, Li, Junjie, Yang, Hong, Jia, Kunpeng, Wu, Zhenhua. HfO2-based Ferroelectric Field-Effect-Transistor with Large Memory Window and Good Synaptic Behavior. ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2021, 10(6): http://dx.doi.org/10.1149/2162-8777/ac08dd.
[9] 张永奎. Comparison of DC/AC Hot Carrier Degradation between Short Channel Si Bulk and SiGe SOI p-FinFETs. 2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)null. 2021, [10] Li, Yangyang, Zhu, Huilong, Kong, Zhenzhen, Zhang, Yongkui, Ai, Xuezheng, Wang, Guilei, Wang, Qi, Liu, Ziyi, Lu, Shunshun, Xie, Lu, Huang, Weixing, Liu, Yongbo, Li, Chen, Li, Junjie, Lin, Hongxiao, Su, Jiale, Zeng, Chuanbin, Radamson, Henry H. The Effect of Doping on the Digital Etching of Silicon-Selective Silicon-Germanium Using Nitric Acids. NANOMATERIALS[J]. 2021, 11(5): http://dx.doi.org/10.3390/nano11051209.
[11] Huilong Zhu. Investigation of ferroelectric FETs using a replacement metal gate process. IOP，Semiconductor Science and Technology. 2021, [12] 张永奎. First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates. Nano Letters[J]. 2021, 21: 4730-4737, [13] Mao, Shujuan, Zhao, Chao, Liu, Jinbiao, Wang, Guilei, Zhang, Yongkui, Wang, Yao, Cui, Hengwei, Liu, Weibing, Li, Menghua, Liu, Yaodong, Zhang, Dan, Xu, Jing, Gao, Jianfeng, Li, Yongliang, Wang, Wenwu, Chen, Dapeng, Li, Junfeng, Ye, Tianchun, Luo, Jun. Experimental Investigation of As Preamorphization Implant on Electrical Property of Ti-Based Silicide Contacts. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2021, 68(4): 1835-1840, http://dx.doi.org/10.1109/TED.2021.3057337.
[14] Zhang, Qingzhu, Tu, Hailing, Zhang, Zhaohao, Li, Junjie, Wei, Feng, Wang, Guilei, Han, Jiaohao, Zhao, Hongbin, Zhang, Yongkui, Li, Yongliang, Wu, Zhenhua, Gu, Jie, Xu, Renren, Bai, Guibin, Xu, Gaobo, Wei, Qianhui, Fan, Yanyan, Yan, Jiang, Li, Bo, Xu, Qiuxia, Yin, Huaxiang, Wang, Wenwu. Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process. MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING[J]. 2021, 121: http://dx.doi.org/10.1016/j.mssp.2020.105434.
[15] Huang, Weixing, Zhu, Huilong, Zhang, Yongkui, Li, Junjie, Ai, Xuezheng, Yin, Xiaogen, Li, Chen, Li, Yangyang, Li, Xinhao, Jia, Kunpeng, Xiang, Jinjuan, Xu, Gaobo. Investigation of ferroelectric field-effect transistors using a replacement metal gate process. SEMICONDUCTOR SCIENCE AND TECHNOLOGY[J]. 2021, 36(3): http://dx.doi.org/10.1088/1361-6641/abcee3.
[16] Gu, Jie, Zhang, Qingzhu, Wu, Zhenhua, Yao, Jiaxin, Zhang, Zhaohao, Zhu, Xiaohui, Wang, Guilei, Li, Junjie, Zhang, Yongkui, Cai, Yuwei, Xu, Renren, Xu, Gaobo, Xu, Qiuxia, Yin, Huaxiang, Luo, Jun, Wang, Wenwu, Ye, Tianchun. Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs. NANOMATERIALS[J]. 2021, 11(2): https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7911106/.
[17] Zhang, Yongkui, Ai, Xuezheng, Yin, Xiaogen, Zhu, Huilong, Yang, H, Wang, G L, Li, J J, Du, A Y, Li, C, Huang, W X, Xie, L, Li, Y Y, Liu, Y B, Zhang, Y B, Jia, K P, Wu, Z H, Ma, X L, Zhang, Q Z, Mao, S J, Xu, G B, Xiang, J J, Gao, J F, He, X B, Lu, Y H, Bai, G B, Zhao, J, Li, Y L, Yang, T, Li, J F, Yin, H X, Radamson, H, Luo, J, Zhao, C, Wang, W W, Ye, T C. Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2021, 68(6): 2604-2610, http://dx.doi.org/10.1109/TED.2021.3072879.
[18] Xie, Lu, Zhu, Huilong, Zhang, Yongkui, Ai, Xuezheng, Li, Junjie, Wang, Guilei, Du, Anyan, Kong, Zhenzhen, Wang, Qi, Lu, Shunshun, Li, Chen, Li, Yangyang, Huang, Weixing, Radamson, Henry H. Investigation on Ge0.8Si0.2-Selective Atomic Layer Wet-Etching of Ge for Vertical Gate-All-Around Nanodevice. NANOMATERIALS[J]. 2021, 11(6): [19] Huang, Weixing, Zhu, Huilong, Jia, Kunpeng, Wu, Zhenhua, Yin, Xiaogen, Huo, Qiang, Zhang, Yongkui. Investigation of device-circuit for negative capacitance vertical nanowire FETs based on SPICE model. SEMICONDUCTOR SCIENCE AND TECHNOLOGY[J]. 2020, 35(8): https://www.webofscience.com/wos/woscc/full-record/WOS:000552686400001.
[20] Xie, Lu, Zhu, Huilong, Zhang, Yongkui, Ai, Xuezheng, Wang, Guilei, Li, Junjie, Du, Anyan, Kong, Zhenzhen, Yin, Xiaogen, Li, Chen, Zhao, Liheng, Li, Yangyang, Jia, Kunpeng, Li, Ben, Radamson, Henry H. Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium. NANOMATERIALS[J]. 2020, 10(9): http://dx.doi.org/10.3390/nano10091715.
[21] Yin, Xiaogen, Zhang, Yongkui, Zhu, Huilong, Wang, G L, Li, J J, Du, A Y, Li, C, Zhao, L H, Huang, W X, Yang, H, Xie, L, Ai, X Z, Zhang, Y B, Jia, K P, Wu, Z H, Ma, X L, Zhang, Q Z, Mao, S J, Xiang, J J, 高建峰, He, X B, Bai, G B, Lu, Y H, Zhou, N, Kong, Z Z, Zhang, Y, Zhao, J, Ma, S S, Xuan, Z H, Li, Y Y, Li, L, Zhang, Q H, Han, J H, Chen, R L, Qu, Y, Yang, T, Luo, J, Li, J F, Yin, H X, Radamson, H, Zhao, C, Wang, W W, Ye, T C. Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation. IEEE ELECTRON DEVICE LETTERS[J]. 2020, 41(1): 8-11, https://www.webofscience.com/wos/woscc/full-record/WOS:000507305400002.
[22] Li, Chen, Zhu, Huilong, Zhang, Yongkui, Yin, Xiaogen, Jia, Kunpeng, Li, Junjie, Wang, Guilei, Kong, Zhenzhen, Du, Anyan, Yang, Tengzhi, Zhao, Liheng, Huang, Weixing, Xie, Lu, Li, Yangyang, Ai, Xuezheng, Ma, Shishuai, Radamson, Henry H. Selective Digital Etching of Silicon-Germanium Using Nitric and Hydrofluoric Acids. ACS APPLIED MATERIALS & INTERFACES[J]. 2020, 12(42): 48170-48178, https://www.webofscience.com/wos/woscc/full-record/WOS:000584489800102.
[23] Zhang, Yadong, Jia, Kunpeng, Liu, Jiangtao, Pan, Yu, Luo, Kun, Yu, Jiahan, Zhang, Yongkui, Tian, Hanmin, Wu, Zhenhua, Yin, Huaxiang. The optimization of contact interface between metal/MoS2 FETs by oxygen plasma treatment. JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS[J]. 2020, 31(12): 9660-9665, http://dx.doi.org/10.1007/s10854-020-03511-7.
[24] Yin, Xiaogen, Zhu, Huilong, Zhao, Liheng, Wang, Guilei, Li, Chen, Huang, Weixing, Zhang, Yongkui, Jia, Kunpeng, Li, Junjie, Radamson, Henry H. Study of Isotropic and Si-Selective Quasi Atomic Layer Etching of Si1-xGex. ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2020, 9(3): https://www.webofscience.com/wos/woscc/full-record/WOS:000522881000001.
[25] Huang, Weixing, Zhu, Huilong, Wu, Zhenhua, Yin, Xiaogen, Huo, Qiang, Jia, Kunpeng, Li, Yangyang, Zhang, Yongkui. Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY[J]. 2020, 8: 879-884, https://doaj.org/article/307c1eaab704467ba5f2bf88741a7fbc.
[26] Li Chen, Zhu Huilong, Zhang Yongkui, Yin Xiaogen, Jia Kunpeng, Li Junjie, Wang Guilei, Kong Zhenzhen, Du Anyan, Yang Tengzhi, Zhao Liheng, Xie Lu, Ai Xuezheng, Ma Shishuai, Li Yangyang, Radamson Henry H, Li Chen, Zhu Huilong, Zhang Yongkui, Yin Xiaogen, Jia Kunpeng, Li Junjie, Wang Guilei, Kong Zhenzhen, Du Anyan, Yang Tengzhi, Zhao Liheng, Xie Lu, Ai Xuezheng, Ma Shishuai, Li Yangyang, Radamson Henry H. A Study of Selectively Digital Etching Silicon-Germanium with Nitric and Hydrofluoric Acids. 2020, http://arxiv.org/abs/2003.03529.
[27] Li, Junjie, Li, Yongliang, Zhou, Na, Wang, Guilei, Zhang, Qingzhu, Du, Anyan, Zhang, Yongkui, Gao, Jianfeng, Kong, Zhenzhen, Lin, Hongxiao, Xiang, Jinjuan, Li, Chen, Yin, Xiaogen, Li, Yangyang, Wang, Xiaolei, Yang, Hong, Ma, Xueli, Han, Jianghao, Zhang, Jing, Hu, Tairan, Yang, Tao, Li, Junfeng, Yin, Huaxiang, Zhu, Huilong, Wang, Wenwu, Radamson, Henry H. A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm. MATERIALS[J]. 2020, 13(3): https://doaj.org/article/6d27beb2892d4c24b1b1988ad2b46a06.
[28] Huang, Weixing, Zhu, Huilong, Jia, Kunpeng, Yin, Xiaogen, Li, Chen, Zhang, Yongkui, Xiang, Jinjuan, Wu, Zhenhua, Gan, Lurong. Simulations of VNW-FETs with Adjustable Spacer-Like Negative Capacitors Based on Experimental Data. ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2019, 8(2): Q38-Q42, https://www.webofscience.com/wos/woscc/full-record/WOS:000460604800002.
[29] Zhao, Zhiqian, Li, Yongliang, Wang, Guilei, Du, Anyan, Li, Yan, Zhang, Qingzhu, Xu, Gaobo, Zhang, Yongkui, Luo, Jun, Li, JunFeng, Wang, Wenwu. Process optimization of the Si0.7Ge0.3 Fin Formation for the STI first scheme. SEMICONDUCTOR SCIENCE AND TECHNOLOGY[J]. 2019, 34(12): https://www.webofscience.com/wos/woscc/full-record/WOS:000494668200001.
[30] Zhang, Yadong, Liu, Jiangtao, Pan, Yu, Luo, Kun, Yu, Jiahan, Zhang, Yongkui, Jia, Kunpeng, Yin, Huaxiang, Zhu, Huilong, Tian, Hanmin, Wu, Zhenhua. The evolution of MoS2 properties under oxygen plasma treatment and its application in MoS2 based devices. JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS[J]. 2019, 30(19): 18185-18190, http://dx.doi.org/10.1007/s10854-019-02172-5.
[31] Zhang, Zhaohao, Xu, Gaobo, Zhang, Qingzhu, Hou, Zhaozhao, Li, Junjie, Kong, Zhenzhen, Zhang, Yongkui, Xiang, Jinjuan, Xu, Qiuxia, Wu, Zhenhua, Zhu, Huilong, Yin, Huaxiang, Wang, Wenwu, Ye, Tianchun. FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2. IEEE ELECTRON DEVICE LETTERS[J]. 2019, 40(3): 367-370, [32] Xu, Miao, Zhu, Huilong, Zhang, Yanbo, Xu, Qiuxia, Zhang, Yongkui, Qin, Changliang, Zhang, Qingzhu, Yin, Huaxiang, Xu, Hao, Chen, Shuai, Luo, Jun, Li, Chunlong, Zhao, Chao, Ye, Tianchun. Two methods of tuning threshold voltage of bulk FinFETs with replacement high-k metal-gate stacks. SOLID-STATE ELECTRONICS[J]. 2017, 129: 52-60, http://dx.doi.org/10.1016/j.sse.2016.12.016.
[33] Zhang Qingzhu, Yin Huaxiang, Luo Jun, Yang Hong, Meng Lingkuan, Li Yudong, Wu Zhenhua, Zhang Yanbo, Zhang Yongkui, Qin Zhangliang, Li Junjie, Gao Jianfeng, Wang Guilei, Xiong Wenjuan, Xiang Jinjuan, Zhou Zhangyu, Mao Shujuan, Xu Gaobo, Liu Jinbiao, Yang Tao. FOI FinFET with Ultra-low Parasitic Resistance Enabled by Fully Metallic Source and Drain Formation on Isolated Bulk-Fin. 2016 IEEE International Electron Devices Meeting: IEDM 2016, San Francisco, California, USA, 3-7 December 2016, pages 452-929, v.2null. 2016, 452-455, http://159.226.55.106/handle/172511/16336.
[34] 赵治国, 张永奎, 朱慧珑, 张严波, 秦长亮, 张青竹, 张月, 赵超, 存储器研发中心. 小尺寸器件的金属栅平坦化新技术. 真空科学与技术学报[J]. 2016, 36(9): 1030-1033, http://159.226.55.106/handle/172511/16102.
[35] Zhang, Yanbo, Zhu, Huilong, Wu, Hao, Zhang, Yongkui, Zhao, Zhiguo, Zhong, Jian, Yang, Hong, Liang, Qingqing, Wang, Dahai, Li, Junfeng, Jia, Cheng, Liu, Jinbiao, Zhao, Yuyin, Li, Chunlong, Meng, Lingkuan, Hong, Peizhen, Li, Junjie, Xu, Qiang, Gao, Jianfeng, He, Xiaobin, Lu, Yihong, Zhang, Yue, Yang, Tao, Wang, Yao, Cui, Hushan, Zhao, Chao, Yin, Huaxiang, Zhong, Huicai, Yin, Haizhou, Yan, Jiang, Wang, Wenwu, Chen, Dapeng, Yu, Hongyu, Yang, Simon, Ye, Tianchun. Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2015, 62(5): 1411-1418, http://www.irgrid.ac.cn/handle/1471x/1091057.
[36] Xu Miao, Yin Huaxiang, Zhu Huilong, Ma Xiaolong, Xu Weijia, Zhang Yongkui, Zhao Zhiguo, Luo Jun, Yang Hong, Li Chunlong, Meng Lingkuan, Hong Peizheng, Xiang Jinjuan, Gao Jianfeng, Xu Qiang, Xiong Wenjuan, Wang Dahai, Li Junfeng, Zhao Chao, Chen Dapeng, Yang Simon, Ye Tianchun. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs. JOURNAL OF SEMICONDUCTORS[J]. 2015, 36(4): 044007-1, http://www.irgrid.ac.cn/handle/1471x/1091059.

   

（ 1 ） 新型纳米线晶体管及应用研究（二期）, 参与, 部委级, 2020-05--2022-04
（ 2 ） 14纳米FinFET工艺技术研发, 参与, 院级, 2017-03--2021-12
（ 3 ） 3-1纳米集成电路先导工艺预研, 参与, 部委级, 2019-08--2022-12
（ 4 ） 水平堆叠环栅器件研制与新型沟道原型器件研究, 参与, 省级, 2019-07--2021-06
（ 5 ） 垂直围栅纳米晶体管DRAM存储器器件与工艺研发, 参与, 省级, 2021-04--2023-12