发表论文
[1] Zou Kaiwei, Wang Ying, Cheng Long, Qu Songyun, Li Huawei, Li Xiaowei. CAP: Communication-aware Automated Parallelization for Deep Learning Inference on CMP Architectures. IEEE TRANSACTIONS ON COMPUTERS[J]. 2022, 71(7): 1626-1639, [2] He Yintao, Wang Ying, Li Huawei, Li Xiaowei. Saving Energy of RRAM-based Neural Accelerator through State-Aware Computing. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2022, 41(7): 2115-2127, [3] Liang, Shengwen, Wang, Ying, Liu, Cheng, He, Lei, Li, Huawei, Xu, Dawen, Li, Xiaowei. EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. IEEE TRANSACTIONS ON COMPUTERS[J]. 2021, 70(9): 1511-1525, [4] 王颖. An Automated Quantization Framework for High-utilization RRAM-based PIM. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2021, [5] Cheng, Long, Wang, Ying, Liu, Qingzhi, Epema, Dick H J, Liu, Cheng, Mao, Ying, Murphy, John. Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS[J]. 2021, 32(6): 1494-1510, http://dx.doi.org/10.1109/TPDS.2021.3053241.[6] Cheng, Yun, Li, Huawei, Wang, Ying, Li, Xiaowei. Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2019, 38(4): 767-779, http://dx.doi.org/10.1109/TCAD.2018.2818690.[7] Wang, Ying, Li, Huawei, Cheng, Long, Li, Xiaowei. A QoS-QoR Aware CNN Accelerator Design Approach. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2019, 38(11): 1995-2007, http://dx.doi.org/10.1109/TCAD.2018.2877010.[8] Shi, Cong, Li, Jiajun, Wang, Ying, Luo, Gang. Exploiting Lightweight Statistical Learning for Event-Based Vision Processing. IEEE ACCESS[J]. 2018, 6: 19396-19406, https://doaj.org/article/5c6584ce90a8465db22b57429190df95.[9] 王颖. Resilience-Aware Frequency Tuning for Neural-Network based Approximate Computing Chips. IEEE Transactions on Very Large Scaled Integration Systems. 2018, [10] 王颖. A Low Overhead In-Network Data Compressor for the Memory Hierarchicy of Chip Multi-Processors. IEEETRANSACTIONSONCOMPUTERAIDEDDESIGNOFINTEGRATEDCIRCUITSANDSYSTEMS. 2018, [11] Lian Shiqi, Han Yinhe, Chen Xiaoming, Wang Ying, Xiao Hang, IEEE. Dadu-P: A Scalable Accelerator for Robot Motion Planning in a Dynamic Environment. 2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC)null. 2018, http://dx.doi.org/10.1145/3195970.3196020.[12] Wang, Ying, Quan, Zhenyu, Li, Jiajun, Han, Yinhe, Li, Huawei, Li, Xiaowei, IEEE. A Retrospective Evaluation of Energy-Efficient Object Detection Solutions on Embedded Devices. PROCEEDINGSOFTHE2018DESIGNAUTOMATIONTESTINEUROPECONFERENCEEXHIBITIONDATEnull. 2018, 709-714, [13] Cheng, Yun, Li, Huawei, Wang, Ying, Shen, Haihua, Liu, Bo, Li, Xiaowei. On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2018, 37(10): 2166-2179, https://www.webofscience.com/wos/woscc/full-record/WOS:000445264200020.[14] 王颖. A Case of On-chip memory Sub-system Design for Low-Power Machine Learning Accelerators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018, [15] Wang, Ying, Han, YinHe, Wang, Cheng, Li, Huawei, Li, Xiaowei. Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2017, 36(5): 705-718, [16] Li Huawei. Approximate STT-RAM Buffer Design for General Purpose Neural Network Accelerator. IEEE Transactions on Very Large Scaled Integration Systems. 2017,