Analog/RF and Mixed-Signal Integrated Circuits

  - High-speed IC for optical communications

  - CMOS wireless/wireline IC

  - CMOS sensor IC for ToF laser ranging

B.S.     Dpt. of mechanical and electronic engineering       Beijing Institute of Technology       2005

M.S.     Institute of Microelectronics                                 Tsinghua University                      2008

Ph.D.    Institute of Microelectronics                                 Tsinghua University                      2013

Post-doctoral associate in both academia and industry in U.S.

Post-doc research scholar    Dpt. of EECS      Oregon State University, OR, USA      2013-2015

Post-doc and senior circuit-design engineer    Hewlett-Packard Labs, CA, USA       2015-2017

"Nonlinear Electronic Circuits"     Autumn-term    Undergraduates    UCAS

"High-speed Circuits Design for Photonic-Electronic Integrated Chips"    Spring-term   Post-graduates    UCAS

   

Selected Journal Papers (* for corresponding author)

1. Q. Liao, Y. Zhang, S. Ma, L. Wang, G. Li, Z. Zhang, J. Liu, N. Wu, L. Liu, Y. Chen, X. Xiao* and N. Qi*, “A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR,” IEEE J. Solid-State Circuits (JSSC), vol. 57, no. 3, pp. 767–780, March 2022.

2. Q. Liao, N. Qi*, M. Li, S. Hu, J. He, B. Yin, J. Shi, J. Liu, P. Y. Chiang, X. Xiao* and N. Wu, “A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 5, pp. 1282–1296, May 2020.

3. J. He, D. Lu, H. Xue, S. Chen, H. Liu, L. Li, G. Li, Z. Zhang, J. Liu, L. Liu, N. Wu, N. Yu, F. Liu, X. Xiao, Y. Chen and N. Qi*, “Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects,” IEEE Trans. Circuits Syst. I Regul. Pap. (TCAS-I), vol. 69, no. 11, pp. 4345–4357, Nov. 2022.

4. J. He, Y. Zhang, H. Liu, Q. Liao, Z. Zhang, M. Li, F. Jiang, J. Shi, J. Liu, N. Wu, Y. Chen, P. Y. Chiang, N. Yu, X. Xiao and N. Qi*, “A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS,” IEEE Trans. Circuits Syst. I Regul. Pap. (TCAS-I), vol. 69, no. 3, pp. 1159–1170, March 2022.

5. J. Shi*, M. Jin, T. Yang, H. Shu, F. Yang, H. Liu, Y. Tao, J. Deng, R. Chen, C. Han, N. Qi* and X. Wang*, “16-channel photonic–electric co-designed silicon transmitter with ultra-low power consumption,” Photonics Research, vol. 11, no. 2, p. 143, Feb. 2023.

6. H. Zhang, M. Li, Y. Zhang, D. Zhang, Q. Liao, J. He, S. Hu, B. Zhang, L. Wang, X. Xiao*, N. Qi* and S. Yu, “800 Gbit/s transmission over 1 km single-mode fiber using a four-channel silicon photonic transmitter,” Photonics Research, vol. 8, no. 11, p. 1776, Nov. 2020.

7. S. Hu, R. Bai, X. Wang, T. Xia, J. Ma, L. Wang, Y. Zhang, X. Chen, N. Qi* and P. Y. Chiang, “A 4×25 Gb/s Optical Transmitter Using Low-Cost 10 Gb/s VCSELs in 40-nm CMOS,” IEEE Photonics Technol. Lett. (PTL), vol. 31, no. 12, pp. 967–970, 2019.

8. J. Shi, B. Yin, N. Qi*, R. Bai, Z. Li, Z. Hong and P. Y. Chiang, “Design Techniques for Signal Reflection Suppression in High-Speed 25-Gb/s Laser Drivers in CMOS,” IEEE Photonics Technol. Lett. (PTL), vol. 30, no. 1, pp. 39–42, 2017.

9. N. Qi*, X. Xiao, S. Hu, X. Li, H. Li, L. Liu, Z. Li, N. Wu and P. Y. Chiang, “Co-Design and Demonstration of a 25-Gb/s Silicon-Photonic Mach Zehnder Modulator With a CMOS-Based High-Swing Driver,” IEEE J. Sel. Top. Quantum Electron. (JSTQE), vol. 22, no. 6, pp. 131–140, Nov./Dec. 2016. 

10. N. Qi*, Y. Xu, B. Chi, Y. Xu, X. Yu, X. Zhang, Ni Xu, Patrick Chiang, Woogeun Rhee, and Zhihua Wang, “A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65nm CMOS with On-Chip I/Q Calibration”, IEEE Trans. Circuits Syst. I Regul. Pap. (TCAS-I), vol. 59, no.8, pp. 1720-1732, Aug. 2012.

11. T. Ma, W. Deng, Z. Chen, J. Wu, W. Zheng, S. Wang, N. Qi, Y. Liu and B. Chi*, “A CMOS 76–81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator,” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 2, pp. 233–248, Feb. 2020.

12. H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. B. Jones, M. Fiorentino, M. Horchberg, S. Palermo and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 50, no. 12, pp. 3145–3159, Dec. 2015. 

13. J. Cheng, N. Qi, P. Y. Chiang and A. Natarajan, “A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 49, issue 12, pp. 3018-3030, Dec. 2014.

Selected Conference Papers (* for corresponding author)

1. Y. Liu, N. Qi*, X. Xu, W. Li, L. Wang, M. Chen, Q. Cheng, J. Shi, L. Liu, J. Liu, X. Xiao, N. Wu, “A 50Gb/s PAM-4 Optical Receiver with Si- Photonic PD and Linear TIA in 40nm CMOS,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.

2. Q. Liao, S. Hu, J. He, B. Yin, P. Y. Chiang, J. Liu, N. Qi* and N. Wu, “A Dual-28Gb/s Digital-Assisted Distributed Driver with CDR for Optical-DAC PAM4 Modulation in 40nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2019.

3. S. Hu, T. Yao, B. Yin, C. Song1, L. Zhao, J. Wang, L. Wang, R. Bai, X. Wang, T.   Xia, Y. Peng, B. Yao, Y. Li, X. Chen, Q. Pan, N. Qi*, P. Y. Chiang, “A 50Gb/s PAM-4 Retimer CDR+VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die,”  IEEE Opt. Fiber Commun. Conf. (OFC), 2019.

4. C. Liu, B. Yin, T. Yao, N. Qi, et al., “A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation,” in IEEE Proc. Opt. Fiber Commun. Conf. (OFC), 2018.

5. J. Wang, X. Chen, S. Hu, Y. Cai, R. Bai, X. Wang, Y. Zhang, S. Zhuo, L. Chang, B. Yin, J. Ma, H. Yan, J. Xuan, M. Lu, T. Xia, N. Qi* and P. Y. Chiang, “A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS,” IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2018.

6. N. Qi*, et al., “A 51Gb/s, 320mW, PAM4 CDR with Baud-Rate Sampling for High-Speed Optical Interconnects,” IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2017.

7. B. Yin, N. Qi*, et al., “A 32Gb/s-NRZ, 15GBaud/s-PAM4 DFB laser driver with active back-termination in 65nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2017.

8. N. Qi*, et al., “A 32Gb/s NRZ, 25GBaud/s PAM4 Reconfigurable, Si-Photonic MZM Transmitter in CMOS,” in IEEE Proc. Opt. Fiber Commun. Conf. (OFC), 2016.

9. N. Qi*, et al., “A 25Gb/s, 520mW, 6.4Vpp Silicon-Photonic Mach-Zehnder Modulator with Distributed Driver in CMOS,” in IEEE Proc. Opt. Fiber Commun. Conf. (OFC), 2015.

10. H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, et al., “A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS,” in Dig. IEEE Int. Solid-State Circuit Conf. (ISSCC), Feb. 2015.

11. J. Cheng, N. Qi, et al., “A 1.3mW 0.6V WBAN-Compatible Sub-Sampling PSK Receiver in 65nm CMOS,” in Dig. IEEE Int. Solid-State Circuit Conf. (ISSCC), Feb. 2014.

12. N. Qi, et al., “An Asymmetric Dual-Channel Reconfigurable Receiver for GNSS in 180nm CMOS”, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2013.

13. N. Qi, et al., “An 180nm Fully-Integrated Dual-Channel Reconfigurable Receiver for GNSS Interoperations,” in Proc. of European Solid-State Circuits Conf. (ESSCIRC), 2013.

14. N. Qi, et al., “A multi-mode blocker-tolerant GNSS receiver with CT sigma delta ADC in 65nm CMOS,” in IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2013.

15. N. Qi, et al., “A Multi-Mode Complex Bandpass Filter With   gm-Assisted Power Optimization and I/Q Calibration”, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2013.

16. N. Qi, et al., “A dual-channel   GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC) 2011.

Nan Qi, Cheng Li and Marco Fiorentino, “Signal control for segmented modulators,” PCT/US2015/057680. Nan Qi, Cheng Li and Marco Fiorentino, “Optical modulator drivers,”   PCT/US2015/057870.

A.      CMOS High-Speed ICs for Silicon-Photonic Communication

- CMOS/BiCMOS Driver, TIA at 56Gb/s and above

- Monolithic integration of driver/modulator, PD/TIA at 25Gb/s and above

         

         

         

B.      CMOS ICs for D-ToF 3D-Sensors

- APD/SPAD based sensor ICs with TDC/ADCs

- Laser driver with fast rising/falling transient

         

     128 pixels SPAD array w/t TDC (2018)           Single TDC w/t PLL (2019)

C.     CMOS Wireline/Wireless ICs for Communication

- CMOS CDR, SERDES at 25Gb/s and above

        - CMOS GPS/Beidou RF-Receivers

    

    

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