1. 毫米波、太赫兹收发机及相控阵芯片设计研究

2. 高速光/Serdes互联芯片及高密度片间互联芯片设计研究

3. 高性能时钟产生及分布电路设计研究

每年招收博士生1名，硕士生1名

140100-集成电路科学与工程
080903-微电子学与固体电子学
080902-电路与系统

光电互联芯片设计
时钟产生及分布电路设计
毫米波及太赫兹感知及通信芯片设计

2016-09--2021-11   香港科技大学   博士学位
2012-09--2016-08   华中科技大学   学士学位

工作经历：

2021~2024，香港科技大学，博士后研究员

2025~今，中国科学院微电子研究所，青年研究员

入选中国科学院高层次青年人才项目

​入选国家自然科学基金优秀青年科学基金项目（海外）

学术兼职：

2025-11, IEEE国际集成电路与系统论坛 (ISICAS)，有线通信分会主席

2025-02-09-今,IEEE Transactions on Circuits and Systems Part I (TCAS-I), 审稿人

2024-01-16-今,IEEE Transactions on Microwave Theory and Techniques, 审稿人

2023-05-31-今,IEEE Journal of Solid-State Circuits, 审稿人

2022-04-12-今,IEEE Solid-State Circuits Letters, 审稿人

专利：

1. C. Patrick Yue, and Li Wang, "PAM-4 receiver with jitter compensation clock and data recovery." U.S. Patent Application, No. 17/744,743.

2. C. Patrick Yue, and Li Wang, “A 28-GHz Phased-Array Transmitter Based on IFLO Phase-Shifting Architecture Supporting Complete Orthogonality between Phase Shift and Gain Control,” US Provisional Patent, No. 63/518,882.

3. C. Patrick Yue, Li Wang, “Cascaded Dual-Loop PLL for Lowered Phase Noise with Improved Tuning Range,” US Provisional Patent, No. 63/637,898.

4. 王力，俞捷，一种高线性度低噪声光接收机前端，CN116192274A, 2023-05-30.

5. 俞捷，王力，具有抖动补偿时钟和数据恢复的PAM-4接收器，CN115378564A, 2022-11-22.

(1) Compact 28-GHz Transmitter Front End With Co-Optimized Wideband Chip-to-Antenna Interface, IEEE Transactions on Microwave Theory and Techniques (TMTT), 2025, 通讯作者

(2) A 28-GHz Phased-Array Transmitter Achieving 24% Peak Efficiency, 0.26-mm2/ Element Area Efficiency with Completely Orthogonal Phase and Gain Control, 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024, 第 1 作者

(3) A compact 20-24-GHz sub-sampling PLL with charge-domain bandwidth control scheme, IEEE Journal of Solid-State Circuits (JSSC), 2024, 第 1 作者

(4) A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitter, 2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, 第 1 作者

(5) A 60-Gb/s 1.2-pJ/bit 1/4-rate PAM-4 receiver with a jitter compensation CDR, IEEE Journal of Solid-State Circuits (JSSC), 2023, 第 1 作者

(6) A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and -248.6-dB FoM_jitter, 2023 Symposium on VLSI Circuits (VLSI), 2023, 第 1 作者

(7) A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a-8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery, 2021 Symposium on VLSI Circuits (VLSI), 2021, 第 1 作者

(8) A 75-Mb/s RGB PAM-4 visible light communication transceiver system with pre-and post-equalization, Journal of Lightwave Technology (JLT), 2021, 第 1 作者

(9) Simultaneous magnetic resonance wireless power and high-speed data transfer system with cascaded equalizer for variable channel compensation, IEEE Transactions on Power Electronics (TPE), 2019, 第 1 作者

(10) A dual-resonance matching circuit for magnetic resonance wireless power transfer systems, 2019 IEEE Global Conference on Consumer Electronics (GCCE), 2019, 第 1 作者

(11) Smart Table Applications Based on Magnetic Resonance Wireless Power Transfer, 2019 IEEE Global Conference on Consumer Electronics (GCCE), 2019, 第 1 作者

(12) Modulation optimization for visible laser light communication systems, 2017 IEEE Photonics Conference (IPC), 2017, 第 1 作者

(13) Mechanically tunable terahertz graphene plasmonics using soft metasurface, 2D Materials, 2016, 第 1 作者

谷歌学术链接：‬https://scholar.google.com/citations?user=yttJxGsAAAAJ&hl=en

(1) 中国科学院高层次青年人才项目，项目负责人，2026.01~2028.12

(2) 国家高层次青年人才项目，项目负责人，2026.01~2018.12