Electronic Design Automation (EDA), AI for EDA

Domain-Specific Architecture, AI for XPU design

Approximate computing, Fault-tolerant computing

CCF Fellow, IEEE Senior Member

Oct. 2008- present, Professor, ICT, CAS

Aug. 2009- Aug. 2010, Visiting Professor, University of California at Santa Barbara, USA

Oct. 2001- Oct. 2008, Associate Professor, ICT, CAS

July 2001- Sept. 2001, Assistant Professor, ICT, CAS

Part-Time Positions:

Chair, Technical Committee on Integrated Circuit Design, China Computer Federation

Vice Chair and Secretary General, VLSI Testing Committee, Chinese Society on Measurement

Associate Editor, IEEE Design & Test, since 2022

Associate Editor, IEEE Transactions on Very Large Scale Integration Systems, since 2015

Associate Editor, Journal of Computer Science and Technology, since 2022

Associate Editor, Journal of Computer Research and Development, since 2014

1. National Technology Invention Award, the State Council of the People's Republic of China, 2012

2. CCF Science and Technology Award, from China Computer Federation, 2021

3. Beijing Science and Technology Award, from Beijing Government, 2014, 2017, 2020

4. China Quality Technical Award, China Quality Association, 2011

5. Lu Jia-Xi Young Scientist Award, from Chinese Academy of Sciences, 2008

6. Beijing Science and Technology Award, from Beijing Government, 2007, 2008

7. Outstanding Science and Technology Achievement (Honor), for my prominent achievement in the Goodson CPU, from Chinese Academy of Sciences, 2003

8. Microsoft Fellowship, from the Microsoft Research, China, 2001

9. Special President Scholarship, from Chinese Academy of Sciences, 2001

Selected Journal Papers:

[1] Kaiyan Chang, Mingzhi Chen, Yunji Chen, et al., “Large processor chip model,” Science China Inf. Sci. (SCIS), 2026, Vol. 69, No. 5, Article 153401, 2026.

[2] Kaiyan Chang, Yiming Gan, Wenlong Zhu, Kun Wang, Zhirong Chen, Yuan Cheng, Yinhe Han, Huawei Li, and Ying Wang, “ScaleGS: Closing the Gap between Real-time 3D Gaussian Splatting and Real-time XR Rendering,” ACM Trans. Archit. Code Optim. (TACO), Vol.22, No.4, Article 150, 2025.

[3] Yintao He, Bin Li, Ying Wang, Cheng Liu, Huawei Li and Xiaowei Li, "A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.43, No.9, pp.2635-2646, 2024.

[4] Xiaoze Lin, Liyang Lai and Huawei Li, "Parallel Static Learning Toward Heterogeneous Computing Architectures," IEEE TCAD, Vol.43, No.3, pp.983-993, 2024.

[5] Wen Li, Ying Wang, Cheng Liu, Yintao He, Lian Liu, Huawei Li, Xiaowei Li, “On-line Fault Protection for ReRAM-based Neural Networks,” IEEE Transactions on Computers (TC),Vol.72, No.2, pp.423-437, 2023.

[6] Kaiwei Zou, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, “CAP: Communication-aware Automated Parallelization for Deep Learning Inference on CMP Architectures,” IEEE TC, Vol.71, No.7, pp. 1626 - 1639, 2022.

[7] Yintao He, Ying Wang, Huawei Li, Xiaowei Li, "Saving Energy of RRAM-based Neural Accelerator through State-Aware Computing,” IEEE TCAD, Vol.41, No.7, pp. 2115 - 2127, 2022.

[8] Ying Wang, Yintao He, Long Cheng, Huawei Li, Xiaowei Li, "A Fast Precision Tuning Solution for Always-On DNN Accelerators,” IEEE TCAD, Vol.41, No.5, pp.1236-1248, 2022.

[9] Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li, “EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks,” IEEE Transactions on Computers (TC), Vol.70, No.9 pp. 1511-1525, 2021. (BEST PAPER AWARD)

[10] Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li, “An Edge 3D CNN Accelerator for Low Power Activity Recognition,” IEEE TCAD, Vol.40, No.5, pp.918-930, 2021.

[11] Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li, “A Guaranteed Secure Scan Design based on Test Data Obfuscation by Cryptographic Hash,” IEEE TCAD, Vol.39, No.12, pp.4524-4536, Dec. 2020.

[12] Liyang Lai, Hans Tsai, Huawei Li, “GPGPU-based ATPG System: Myth or Reality?” IEEE TCAD, Vol.39, No.1, pp.239-247, 2020.

[13] Ying Wang, Huawei Li, Long Cheng, Xiaowei Li, "A QoS-QoR Aware CNN Accelerator Design Approach,” IEEE TCAD, Vol.38, No.11, pp. 1995-2007, 2019. 

[14] Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li, “Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug,” IEEE TCAD, Vol.38, No.4, pp.767-779, 2019. 

[15] Ying Wang, Huawei Li, Xiaowei Li, “A Case of On-chip Memory Sub-system Design for Low-Power CNN Accelerators,” IEEE TCAD, Vol.37, No.10, pp.1971-1984, 2018. 

[16] Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “On Trace Buffer Reuse based Trigger generation in Post Silicon Debug,” IEEE TCAD, Vol.37, No.10, pp.2166-2179, 2018. 

[17] Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li, “A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multi-Processors,” IEEE TCAD, Vol.37, No.6, pp.1265-1277, 2018. 

[18] Haihua Shen, Hua-Zhe Tan, Huawei Li, Feng Zhang, Xiaowei Li, “LMDet: A “Naturalness” Statistical Method for Hardware Trojan Detection,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.26, No.4, pp.720-732, 2018. 

[19] Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, and Xiaowei Li, “Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips,” IEEE TVLSI, Vol. 25, No. 10, pp.2736-2748, 2017. 

[20] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE TCAD, Vol. 36, No.5, pp.705-718, 2017. 

[21] Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE TCAD, Vol. 35, No.2, pp.285-297, 2016. 

[22] Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE TCAD, Vol. 35, No.6, pp.999-1011, 2016. 

[23] Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors,” IEEE TC, Vol. 65, No.3, pp.716-729, 2016. 

[24] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Data Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE TVLSI, Vol. 23, No.5, pp. 879-892, 2015. 

[25] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE TVLSI, Vol. 23, No.3, pp. 493-506, 2015. 

[26] Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE TVLSI, Vol.22, No.8, pp. 1738-1749, August 2014. 

[27] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE TVLSI, Vol.22, No.1, pp.113-126, 2014. 

[28] Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE TVLSI, Vol.22, No.6, pp. 1450-1455, June 2014. 

[29] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE TVLSI, Vol.21, No.5, May 2013, pp.821-833. 

[30] Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE TVLSI, Vol.21, No.7, July 2013, pp.1220-1233. 

[31] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE TVLSI, Vol.21, No.7, July 2013, pp.1210-1219. 

[32] Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE TVLSI, Vol.20, No.2, 2012, pp.236-247. 

[33] Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE TVLSI, Vol.20, No.12, 2012, pp. 2157-2169. 

[34] Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE TVLSI, Vol.20, No.9, 2012, pp.1565-1577. 

[35] Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE TVLSI, Vol.19, No.10, 2011, pp.1787-1800. 

[36] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE TVLSI, Vol.19, No.11, 2011, pp.1969-1982. 

[37] Huawei Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No.2, 2005, pp.181-195. 

[38] Huawei Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,” Journal of Electronic Testing: Theory and Applications(JETTA), Vol.16, No.5, Oct. 2000, pp. 477-485. 

Selected Conference Papers:

[1] Jiaping Tang, Jianan Mu, Zhiteng Chao, Jingzhong Wen, Jing Ye, and Huawei Li, “ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression,” 59th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2026.

[2] Mingjun Wang, Yihan Wen, Yuntao Lu, Fengrui Liu, Yuxiang Zhao, Boyu Han, Jianan Mu, Yibo Lin, Runsheng Wang, Bei Yu, Huawei Li, “CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design,” 14th International Conference on Learning Representations (ICLR), 2026.

[3] Junfeng Gong, Zhiyi Wei, Junying Chen, Cheng Liu, Huawei Li, “From Large to Small: Transferring CUDA Optimization Expertise via Reasoning Graph,”14th ICLR, 2026.

[4] Rengang Zhang, Leyan Wang, Zizhen Liu, Bin Sun, Naixing Wang, Cheng Liu, Jing Ye, Huawei Li, “STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference,” 63rd ACM/IEEE Design Automation Conference (DAC), 2026. (CCF-A)

[5] Tenghui Hua, Huawei Li, Jianan Mu, Jing Ye, Liang Kong, Mingzhe Zhang, “Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE,” 63rd ACM/IEEE DAC, 2026.

[6] Yintao He, Haiyu Mao, Christina Giannoula, Mohammad Sadrosadati, Juan Gómez-Luna, Huawei Li, Xiaowei Li, Ying Wang, and Onur Mutlu, “PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System,” 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2025.

[7] Mingjun Wang, Yihan Wen, Bin Sun, Jianan Mu, Juan Li, Xiaoyi Wang, Jing Ye, Bei Yu, Huawei Li, “Bridging Layout and RTL: Knowledge Distillation based Timing Prediction,” 42nd International Conference on Machine Learning (ICML), , 2025.

[8] Kaiyan Chang, Wenlong Zhu, Shengwen Liang, Huawei Li, and Ying Wang, “LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow,” 58th IEEE/ACM MICRO, 2025.

[9] Kaiyan Chang, Kun Wang, Nan Yang, et al., “Data is all you need: Finetuning LLMs for chip design via an automated design-data augmentation framework,” 61st ACM/IEEE DAC, 2024.

[10] Jianan Mu, Husheng Han, Shangyi Shi, et al., “Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption,” 61st ACM/IEEE DAC, 2024.

[11] Feng Gu, Mingjun Wang, Jianan Mu, et al., “DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism,” 43rd IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2024. (BEST PAPER Nomination)

[12] Wenxing Li, Hongqin Lyu, Shengwen Liang, Ttiancheng Wang, Pengyu Tian and Huawei Li, "Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning," 32nd IEEE Asian Test Symposium (ATS), 2023. (BEST PAPER AWARD)

[13] Cangyuan Li, Ying Wang, Huawei Li and Yinhe Han, "APPEND: Rethinking ASIP Synthesis in the Era of AI," 60th ACM/IEEE DAC, 2023.

[14] Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li, "InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs,” 59th ACM/IEEE DAC, 2022.

[15] Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li, "VStore: In-Storage Graph Based Vector Search Accelerator,” 59th ACM/IEEE DAC, 2022.

[16] Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li, “GLIST: Towards In-Storage Graph Learning,” 47th USENIX Annual Technical Conference (ATC), pp.225-238, 2021.

[17] Yongchen Wang, Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “An Activity Analysis Architecture From Compressed Video Streams,” 58th ACM/IEEE DAC, 2021.

[18] Yintao He, Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning,” 58th ACM/IEEE DAC, 2021.

[19] Lei He, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, “GCiM: A Near-Data Processing Accelerator for Graph Construction,” 58th ACM/IEEE DAC, 2021.

[20] Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo，“Special Session - Test for AI Chips: from DFT to On-line Testing,” 38th IEEE VLSI Test Symposium (VTS), 2021.

[21] Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li “Towards State-Aware Computation in ReRAM Neural Networks,” 57th ACM/IEEE DAC, Article No. 73, 2020.

[22] Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li, “An Efficient Deep Learning Accelerator for Compressed Video Analysis,” 57th ACM/IEEE DAC, Article No. 167, 2020.

[23] Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, “DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators,” 39th IEEE ICCAD, 2020.

[24] Wen Li, Ying Wang, Huawei Li, Xiaowei Li “RRAMedy: Protecting ReRAM-based Neural Network from Permanent and Soft Faults During Its Lifetime,” 37th IEEE International Conference On Computer Design (ICCD), 2019. (BEST PAPER AWARD) 

[25] Yintao He, Ying Wang, Huawei Li, Xiaowei Li “An Agile Precision-Tunable CNN Accelerator based on ReRAM,” 38th IEEE/ACM ICCAD, 2019. 

[26] Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li. “Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval,” 45th USENIX ATC, 2019. 

[27] Yongchen Wang, Ying Wang, Huawei Li, Shi Cong, Xiaowei Li, “Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Activity Recognition,” 56th IEEE/ACM DAC, Article No. 210, 2019. 

[28] Ying Wang, Shenwen Liang, Huawei Li, Xiaowei Li, “A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs,” 56th IEEE/ACM DAC, Article No. 202, 2019. 

[29] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Lightweight Timing Channel Protection for Shared DRAM Controller,” 49th IEEE International Test Conference (ITC), 2018. 

[30] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-Processors,” 2nd IEEE International Test Conference in Asia (ITC-Asia), pp.73-78, 2018. (BEST PAPER AWARD)

[31] Ying Wang, Huawei Li, Xiaowei Li, “Real-Time meets Approximate Computing: An Elastic Deep Learning Accelerator Design with Adaptive Trade-off between QoS and QoR,” 54th  IEEE/ACM DAC, Article No. 33, 2017. 

[32] Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang, “Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking,” 48th IEEE ITC, Paper 11.1, 2017. 

[33] Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family,” 53rd IEEE/ACM DAC, 2016. 

[34] Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li, “DISCO: A Low Overhead In-Network Data Compressor for Energy-Efficient Chip Multi-Processors,” 53rd IEEE/ACM DAC, 2016. 

[35] Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” 47th IEEE ITC, Paper 16.2, 2016. 

[36] Yanhong Zhou, Huawei Li, Tiancheng Wang, et al., “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”34th IEEE VTS, Paper 1B-2, 2016. 

[37] Yuntan Fang, Huawei Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,”31st IEEE VTS, Paper 10B-3, 2013. 

[38] Songwei Pei, Huawei Li, and Xiaowei Li, “A Unified Test Architecture for on-Line and Off-Line Delay Fault Detections", 29th IEEE VTS, pp.272-277, 2011. 

[39] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, and Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing,” 39th International Symposium on Computer Architecture (ISCA), pp.259-270, 2011.

[40] Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” 7th IEEE International Symposium on VLSI Design, Automation and Test, Taiwan, 2011. (Invited Talk)

[41] Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” 41st IEEE ITC, Paper 12.1, 2010. 

[42] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” 28th IEEE VTS, pp.3-8, 2010. 

[43] Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” 24th IEEE VTS, Berkeley, CA, USA, 2006. 

[44] Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” 12th IEEE Asian Test Symposium (ATS), pp.178-183, 2003.

[45] Huawei Li, Zhongcheng Li, and Yinghua Min, “Delay Testing with Double Observations”, 7th IEEE ATS, Singapore, 1998, pp.96-100.

Program Committee Member, in:
    ITC: IEEE International Test Conference

    DAC: IEEE/ACM Design Automation Conference

    VTS: IEEE VLSI Test Symposium

    DATE:  Design, Automation, and Test in Europe 

    ASP-DAC: IEEE Asia and South Pacific Design Automation Conference
   ETS: IEEE European Test Symposium
   ATS: IEEE Asian Test Symposium
   ISVLSI: IEEE Computer Society Annual Symposium on VLSI
   DFT: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
   VLSI-DAT: International Symposium on VLSI Design, Automation and Test
   APCCS: IEEE Asia Pacific Conference on Circuits and Systems
   VDAT: VLSI Design and Test Symposium