发表论文
[1] 马晓晗, 佀畅, 王颖, 刘成, 张磊. NASA: Accelerating Neural Network Design with a NAS Processor. International Symposium on Computer Architecture (ISCA)[J]. 2021, [2] Xu, Dawen, Liu, Cheng, Wang, Ying, Tu, Kaijie, He, Bingsheng, Zhang, Lei. Accelerating Generative Neural Networks on Unmodified Deep Learning Processors-A Software Approach. IEEE TRANSACTIONS ON COMPUTERS[J]. 2020, 69(8): 1172-1184, http://dx.doi.org/10.1109/TC.2020.3001033.[3] Chao, Lu, Peng, Xiaohui, Xu, Zhiwei, Zhang, Lei. Ecosystem of Things: Hardware, Software, and Architecture. PROCEEDINGS OF THE IEEE[J]. 2019, 107(8): 1563-1583, [4] Xu Zhiwei, Peng Xiaohui, Zhang Lei, Li Dong, Sun Ninghui. The Φ-stack for smart web of things. Proceedings of the Workshop on Smart Internet of Things[J]. 2017, [5] Zhang Lei. Economizing TSV Resources in 3D Network-on-Chip Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016, [6] Wang, Ying, Zhang, Lei, Han, YinHe, Li, HuaWei, Li, Xiaowei. Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS[J]. 2015, 23(5): 879-892, https://www.webofscience.com/wos/woscc/full-record/WOS:000355212000008.[7] Li Xiaowei. Thermal-Constrained Scheduling for Interconnect Energy Reduction in 3D Homogeneous MPSoCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013, [8] Cheng, YuanQing, Zhang, Lei, Han, YinHe, Li, XiaoWei. TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY[J]. 2013, 28(1): 119-128, https://www.webofscience.com/wos/woscc/full-record/WOS:000314190600010.[9] Dong Jianbo, Zhang Lei, Han Yinhe, Wang Ying, Li Xiaowei, ACM, IEEE, EDAC. Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation. PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)null. 2011, 972-977, [10] Dong, Jianbo, Zhang, Lei, Han, Yinhe, Yan, Guihai, Li, Xiaowei. Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling. JOURNAL OF SYSTEMS ARCHITECTURE[J]. 2010, 56(10): 534-542, http://www.corc.org.cn/handle/1471x/2411690.[11] Zhang Lei, Yu Yue, Dong Jianbo, Han Yinhe, Ren Shangping, Li Xiaowei, IEEE. Performance-Asymmetry-Aware Topology Virtualization for Defect-tolerant NoC-based Many-core Processors. 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)null. 2010, 1566-1571, [12] Zhang, Lei, Han, Yinhe, Xu, Qiang, Li, Xiao wei, Li, Huawei. On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS[J]. 2009, 17(9): 1173-1186, https://www.webofscience.com/wos/woscc/full-record/WOS:000269155400001.[13] Zhang Lei. A Fault Tolerance Mechanism in Chip Many-core Processors. Tsinghua Science and Technology. 2007,