面向高速率通信及高精度雷达感知应用的射频/毫米波/亚太赫兹CMOS集成电路设计研究

每年计划招生1~2名博士，1~2名硕士。欢迎有志于从事模拟射频集成电路设计研究的同学报考。

模拟射频集成电路设计

140100-集成电路科学与工程

080903-微电子学与固体电子学

2018-08--2022-11   澳门大学   博士
2015-09--2018-07   中国科学院微电子研究所   硕士
2011-09--2015-07   电子科技大学   学士

2025.03-- 现在 中国科学院微电子研究所 青年研究员/副研究员

2023-08--2025-03 澳门大学 博士后研究员

2023-06--2023-08 澳门大学 研究助理

代表性论文

[1] Yunbo Huang, YongChen, Zunsong Yang, Rui P. Martins and Pui-In Mak, “A 0.027mm² 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fs_rms Jitter and −74.2dBc Reference Spur,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, Feb. 2024. [第一作者]

[2] Kai Cheng, Yunbo Huang*, Zunsong Yang*, Li Wang, Hongyu Ren, Xiaoyu Shan, Pui-in Mak, Yong Chen*, Bo Li, “A 65nm 0.066pJ/bit Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, Feb. 2026. [通讯作者]

[3] Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui P. Martins, Yan Lu, Nan Sun, Nan Qi, and Yong Chen, “A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction” IEEE Journal of Solid-State Circuits (JSSC), Nov. 2025. [第一作者]

[4] Yunbo Huang, Zunsong Yang, Li Wang, Kai Cheng, Hongyu Ren, Xiaoyu Shan, Pui-in Mak, Yong Chen, and Bo Li, “A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase Detector Achieving 53.8fsrms Jitter and −281.1dB FoMN” IEEE Symposium on VLSI Technology and Circuits (VLSI), Jun. 2026. [第一作者]

[5] Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui P. Martins, Yan Lu, Nan Sun, Nan Qi, and Yong Chen, “A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and −254.3dB FoM” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2025. [第一作者]

[6] Yunbo Huang, Zunsong Yang, Kai Cheng, Hongyu Ren, Xiaoyu Shan, Li Wang, Yong Chen, Bo Li, “A 7.0-to-8.6GHz Balanced Class-F^-1 VCO with a Trifilar Transformer-Based Tank Achieving 194.5dBc/Hz FoM” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2026. [第一作者]

[7] Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak and Rui P. Martins, “A 3.78-GHz type-I sampling PLL with a fully passive K_PD-doubled primary-secondary S-PD measuring 39.6-fs_RMS jitter, -260.2-dB FOM and -70.96-dBc reference spur,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 4, pp.1463-1475, Apr. 2023. [第一作者]

[8] Yunbo Huang, Yong Chen, Hao Guo, Pui-In Mak and Rui P. Martins, “A 3.3-mW 25.2-to-29.4-GHz current-reuse VCO using a single-turn multi-tap inductor and differential-only switched-capacitor arrays with a 187.6-dBc/Hz FOM,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 67, no. 11, pp. 3704-3717, Nov. 2020. [第一作者]

[9] Yunbo Huang, Yong Chen, Hailong Jiao, Pui-In Mak and Rui P. Martins, “A 3.36-GHz locking-tuned type-I sampling PLL with -78.6-dBc reference spur merging single-path reference-feedthrough-suppression and narrow-pulse-shielding techniques,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 68, no. 9, pp. 3093-3097, Sep. 2021. [第一作者]

[10] Yunbo Huang, Yong Chen, Pui-In Mak and Rui P. Martins, “Universal stability criterion for type-I sampling phase-locked loops,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol.70, no. 4, pp. 1351-1355, Apr. 2023. [第一作者]

[11] Yunbo Huang, Yong Chen, Kaiyuan Yang, Paolo Crovetti, Pui-In Mak and Rui P. Martins, “A 28nm 368fJ/cycle, 0.43%/V supply-sensitivity, FLL-based RC oscillator featuring positive-TC-only resistors and ΔΣM-based trimming,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 70, pp. 3950-3954, Nov. 2023. [第一作者]

谷歌学术链接：https://scholar.google.com/citations?user=-V0n_-cAAAAJ&hl=zh-CN

IEEE Xplore：https://ieeexplore.ieee.org/author/37086866194

(1) 中国科学院高层次青年人才项目，项目负责人，2026.01~2028.12

(2) 北京市“高创计划”-青年人才托举工程，项目负责人，2025.12~2027.12