基本信息
洪培真 女 中国科学院微电子研究所
电子邮件： hongpeizhen@ime.ac.cn
通信地址： 北京市朝阳区北土城西路3号中科院微电子所
邮政编码：
电子邮件： hongpeizhen@ime.ac.cn
通信地址： 北京市朝阳区北土城西路3号中科院微电子所
邮政编码：
招生信息
招生专业
080903-微电子学与固体电子学
招生方向
新型存储器器件与工艺
集成电路工艺
3D NAND器件与工艺
集成电路工艺
3D NAND器件与工艺
教育背景
2014-09--2020-08 中国科学院大学 博士学位
2008-09--2011-07 北京大学 硕士学位
2004-09--2008-07 南开大学 学士学位
2008-09--2011-07 北京大学 硕士学位
2004-09--2008-07 南开大学 学士学位
工作经历
工作简历
2011-07~2022-04,中科院微电子研究所, 副研究员
社会兼职
2022-01-01-2024-12-31,JAD青年编委,
2017-11-01-2022-10-31,中国电子元器件关键材料与技术专业委员会委员,
2017-11-01-2022-10-31,中国电子元器件关键材料与技术专业委员会委员,
教授课程
存储器工艺与器件技术
专利与奖励
专利成果
[1] 霍宗亮, 李春龙, 张瑜, 洪培真, 邹兴奇, 靳磊. 一种三维NAND型铁电存储器、制作方法及操作方法. CN: CN110071116B, 2021-07-27.
[2] 徐秋霞, 周娜, 李俊峰, 洪培真, 许高博, 孟令款, 贺晓彬, 陈大鹏, 叶甜春. 纳米线阵列围栅MOSFET结构及其制作方法. CN: CN108364910B, 2021-01-15.
[3] 霍宗亮, 李春龙, 邹兴奇, 洪培真, 张瑜, 靳磊. 一种三维铁电存储器及其制造方法. CN: CN109920794B, 2020-11-03.
[4] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. CN: CN105742231B, 2020-04-24.
[5] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. CN: CN105742175B, 2019-09-24.
[6] 洪培真, 殷华湘, 徐唯佳, 马小龙, 徐秋霞, 李俊峰, 赵超. 形成级联纳米线的方法. CN: CN105742153B, 2019-09-24.
[7] 李春龙, 霍宗亮, 张瑜, 洪培真, 邹兴奇, 靳磊. 一种铁电存储器、制作方法及操作方法. CN: CN110071115A, 2019-07-30.
[8] 霍宗亮, 李春龙, 张瑜, 洪培真, 邹兴奇, 靳磊. 一种三维NAND型铁电存储器、制作方法及操作方法. CN: CN110071116A, 2019-07-30.
[9] 霍宗亮, 闫亮, 李春龙, 邹兴奇, 洪培真, 张瑜, 靳磊. 一种铁电存储器、铁电存储器的制备方法及控制方法. CN: CN109860304A, 2019-06-07.
[10] 秦长亮, 王桂磊, 洪培真, 尹海洲, 殷华湘, 赵超. 半导体器件制造方法. 中国: CN103855092B, 2018.11.06.
[11] 殷华湘, 洪培真, 孟令款, 朱慧珑. 半导体器件及其制造方法. 中国: CN104112665B, 2018.09.18.
[12] 洪培真, 殷华湘, 朱慧珑, 刘青, 李俊峰, 赵超, 尹海洲. 鳍式场效应晶体管及其假栅的制造方法. 中国: CN105336624B, 2018.07.10.
[13] 李俊杰, 李春龙, 李俊峰, 王文武, 洪培真. 一种自对准接触孔刻蚀工艺方法. 中国: CN104465493B, 2018.06.26.
[14] 秦长亮, 徐强, 洪培真, 殷华湘, 尹海洲, 李俊峰, 赵超. 半导体器件制造方法. 中国: CN104253049B, 2018-11-06.
[15] 秦长亮, 洪培真, 尹海洲, 殷华湘, 李俊峰, 赵超. 半导体器件制造方法. 中国: CN104143534B, 2018-05-15.
[16] 秦长亮, 洪培真, 殷华湘. 半导体器件及其制造方法. 中国: CN103545366B, 2018-02-13.
[17] 李俊杰, 孟令款, 李春龙, 洪培真, 崔虎山, 李俊峰, 赵超. 一种硅深孔刻蚀方法. 中国: CN105584986B, 2018-02-09.
[18] 秦长亮, 殷华湘, 洪培真, 马小龙, 赵超. 堆叠纳米线制造方法. 中国: CN104078324B, 2018-01-02.
[19] 秦长亮, 尹海洲, 殷华湘, 洪培真, 王桂磊, 赵超. 半导体器件制造方法. 中国: CN103855003B, 2017-11-21.
[20] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. 中国: CN105742232A, 2016-07-06.
[21] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. 中国: CN105742239A, 2016-07-06.
[22] 洪培真, 杨涛, 孟令款, 李春龙, 李俊峰, 赵超. 一种MEMS工艺中的刻蚀方法. 中国: CN105329846A, 2016-02-17.
[23] 杨涛, 李亭亭, 洪培真, 李俊峰, 赵超. 一种半导体深孔刻蚀后的工艺监控方法. 中国: CN105304514A, 2016-02-03.
[24] 杨涛, 徐强, 洪培真, 李俊峰, 赵超. 一种硅深孔工艺的监测方法. 中国: CN104944366A, 2015-09-30.
[25] 洪培真, 马小龙, 殷华湘, 徐秋霞, 李俊峰, 赵超. 一种纳米线及阵列的形成方法. 中国: CN104609360A, 2015-05-13.
[26] 朱慧珑, 洪培真, 殷华湘. FinFET及其制造方法. 中国: CN104103517A, 2014.10.15.
[27] 洪培真, 李春龙, 王文武, 李俊峰, 赵超, 朱慧珑. 一种刻蚀方法. 中国: CN104211010A, 2014-12-17.
[28] 秦长亮, 尹海洲, 殷华湘, 洪培真, 王桂磊, 赵超. 半导体器件制造方法. 中国: CN103854978A, 2014-06-11.
[29] 秦长亮, 洪培真, 殷华湘. 半导体器件制造方法. 中国: CN103545212A, 2014-01-29.
[2] 徐秋霞, 周娜, 李俊峰, 洪培真, 许高博, 孟令款, 贺晓彬, 陈大鹏, 叶甜春. 纳米线阵列围栅MOSFET结构及其制作方法. CN: CN108364910B, 2021-01-15.
[3] 霍宗亮, 李春龙, 邹兴奇, 洪培真, 张瑜, 靳磊. 一种三维铁电存储器及其制造方法. CN: CN109920794B, 2020-11-03.
[4] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. CN: CN105742231B, 2020-04-24.
[5] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. CN: CN105742175B, 2019-09-24.
[6] 洪培真, 殷华湘, 徐唯佳, 马小龙, 徐秋霞, 李俊峰, 赵超. 形成级联纳米线的方法. CN: CN105742153B, 2019-09-24.
[7] 李春龙, 霍宗亮, 张瑜, 洪培真, 邹兴奇, 靳磊. 一种铁电存储器、制作方法及操作方法. CN: CN110071115A, 2019-07-30.
[8] 霍宗亮, 李春龙, 张瑜, 洪培真, 邹兴奇, 靳磊. 一种三维NAND型铁电存储器、制作方法及操作方法. CN: CN110071116A, 2019-07-30.
[9] 霍宗亮, 闫亮, 李春龙, 邹兴奇, 洪培真, 张瑜, 靳磊. 一种铁电存储器、铁电存储器的制备方法及控制方法. CN: CN109860304A, 2019-06-07.
[10] 秦长亮, 王桂磊, 洪培真, 尹海洲, 殷华湘, 赵超. 半导体器件制造方法. 中国: CN103855092B, 2018.11.06.
[11] 殷华湘, 洪培真, 孟令款, 朱慧珑. 半导体器件及其制造方法. 中国: CN104112665B, 2018.09.18.
[12] 洪培真, 殷华湘, 朱慧珑, 刘青, 李俊峰, 赵超, 尹海洲. 鳍式场效应晶体管及其假栅的制造方法. 中国: CN105336624B, 2018.07.10.
[13] 李俊杰, 李春龙, 李俊峰, 王文武, 洪培真. 一种自对准接触孔刻蚀工艺方法. 中国: CN104465493B, 2018.06.26.
[14] 秦长亮, 徐强, 洪培真, 殷华湘, 尹海洲, 李俊峰, 赵超. 半导体器件制造方法. 中国: CN104253049B, 2018-11-06.
[15] 秦长亮, 洪培真, 尹海洲, 殷华湘, 李俊峰, 赵超. 半导体器件制造方法. 中国: CN104143534B, 2018-05-15.
[16] 秦长亮, 洪培真, 殷华湘. 半导体器件及其制造方法. 中国: CN103545366B, 2018-02-13.
[17] 李俊杰, 孟令款, 李春龙, 洪培真, 崔虎山, 李俊峰, 赵超. 一种硅深孔刻蚀方法. 中国: CN105584986B, 2018-02-09.
[18] 秦长亮, 殷华湘, 洪培真, 马小龙, 赵超. 堆叠纳米线制造方法. 中国: CN104078324B, 2018-01-02.
[19] 秦长亮, 尹海洲, 殷华湘, 洪培真, 王桂磊, 赵超. 半导体器件制造方法. 中国: CN103855003B, 2017-11-21.
[20] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. 中国: CN105742232A, 2016-07-06.
[21] 洪培真, 徐秋霞, 殷华湘, 李俊峰, 赵超. 形成纳米线阵列的方法. 中国: CN105742239A, 2016-07-06.
[22] 洪培真, 杨涛, 孟令款, 李春龙, 李俊峰, 赵超. 一种MEMS工艺中的刻蚀方法. 中国: CN105329846A, 2016-02-17.
[23] 杨涛, 李亭亭, 洪培真, 李俊峰, 赵超. 一种半导体深孔刻蚀后的工艺监控方法. 中国: CN105304514A, 2016-02-03.
[24] 杨涛, 徐强, 洪培真, 李俊峰, 赵超. 一种硅深孔工艺的监测方法. 中国: CN104944366A, 2015-09-30.
[25] 洪培真, 马小龙, 殷华湘, 徐秋霞, 李俊峰, 赵超. 一种纳米线及阵列的形成方法. 中国: CN104609360A, 2015-05-13.
[26] 朱慧珑, 洪培真, 殷华湘. FinFET及其制造方法. 中国: CN104103517A, 2014.10.15.
[27] 洪培真, 李春龙, 王文武, 李俊峰, 赵超, 朱慧珑. 一种刻蚀方法. 中国: CN104211010A, 2014-12-17.
[28] 秦长亮, 尹海洲, 殷华湘, 洪培真, 王桂磊, 赵超. 半导体器件制造方法. 中国: CN103854978A, 2014-06-11.
[29] 秦长亮, 洪培真, 殷华湘. 半导体器件制造方法. 中国: CN103545212A, 2014-01-29.
出版信息
发表论文
[1] 洪培真. Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solution. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE[J]. 2022, 37(25007): 1-6, [2] 洪培真. Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solution. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE[J]. 2022, 37(25007): 1-6, [3] 洪培真. 垂直沟道三维存储器控制栅阶梯工艺研究. 2020, [4] Hong, Peizhen, Zhao, Zhiguo, Luo, Jun, Xia, Zhiliang, Su, Xiaojing, Zhang, Libin, Li, Chunlong, Huo, Zongliang. An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND. IEEE ACCESS[J]. 2020, 8: 140054-140061, https://doaj.org/article/e9da23ff1a4543e3bc9c99f11603f5dc.
[5] 洪培真. 垂直沟道三维存储器控制栅阶梯工艺研究. 2020, [6] Hong, Peizhen, Zhao, Zhiguo, Luo, Jun, Xia, Zhiliang, Su, Xiaojing, Zhang, Libin, Li, Chunlong, Huo, Zongliang. An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND. IEEE ACCESS[J]. 2020, 8: 140054-140061, https://doaj.org/article/e9da23ff1a4543e3bc9c99f11603f5dc.
[7] Hong, Peizhen, Xia, Zhiliang, Yin, Huaxiang, Li, Chunlong, Huo, Zongliang. A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme). ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2019, 8(10): P567-P572, https://www.webofscience.com/wos/woscc/full-record/WOS:000488211700001.
[8] Hong, Peizhen, Xia, Zhiliang, Yin, Huaxiang, Li, Chunlong, Huo, Zongliang. A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme). ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2019, 8(10): P567-P572, https://www.webofscience.com/wos/woscc/full-record/WOS:000488211700001.
[9] Qin, Changliang, Yin, Huaxiang, Wang, Guilei, Hong, Peizhen, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Yin, Haizhou, Zhong, Huicai, Yan, Jiang, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Zhao, Chao, Radamson, Henry H. Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs. MICROELECTRONIC ENGINEERING[J]. 2017, 181: 22-28, http://dx.doi.org/10.1016/j.mee.2017.07.001.
[10] Qin, Changliang, Yin, Huaxiang, Wang, Guilei, Hong, Peizhen, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Yin, Haizhou, Zhong, Huicai, Yan, Jiang, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Zhao, Chao, Radamson, Henry H. Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs. MICROELECTRONIC ENGINEERING[J]. 2017, 181: 22-28, http://dx.doi.org/10.1016/j.mee.2017.07.001.
[11] Zou Xingqi, Xia Zhiliang, Jin Lei, Zhang Yu, Jiang Dandan, Li Dong Hua, Xu Qiang, Hong Peizhen, Zeng Ming, Gao Jing, Tang Zhaoyun, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Simulation on Threshold Voltage of L-Shaped Bottom Select Transistor in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1122-1124, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000318.
[12] 孟令款, 洪培真, 贺晓彬, 李春龙, 李俊杰, 李俊峰, 赵超, 韦亚一, 闫江. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devicesLingkuan. Applied Surface Science[J]. 2016, http://159.226.55.106/handle/172511/16218.
[13] Meng, Lingkuan, Hong, Peizhen, He, Xiaobin, Li, Chunlong, Li, Junjie, Li, Junfeng, Zhao, Chao, Wei, Yayi, Yan, Jiang. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices. APPLIED SURFACE SCIENCE[J]. 2016, 362: 483-489, http://dx.doi.org/10.1016/j.apsusc.2015.11.139.
[14] Qin, Changliang, Wang, Guilei, Hong, Peizhen, Liu, Jinbiao, Yin, Huaxiang, Yin, Haizhou, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Xiang, Jinjuan, Zhong, Huicai, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Yan, Jian, Zhao, Chao, Radamson, Henry H. Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs. SOLID-STATE ELECTRONICS[J]. 2016, 123: 38-43, http://dx.doi.org/10.1016/j.sse.2016.05.017.
[15] Jiang Dandan, Xia Zhiliang, Jin Lei, Zhang Yu, Zou Xingqi, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Gao Jing, Zeng Ming, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Impact of Critical Geometry Dimension on Channel Boosting Potential in 3D NAND Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1248-1250, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000355.
[16] Zhang Yu, Jin Lei, Xia Zhiliang, Jiang Dandan, Zou Xingqi, Xu Qiang, Hong Peizhen, Tang Zhaoyun, Zeng Ming, Gao Jing, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. String Select Transistor Leakage Suppression by Threshold Voltage Modulation in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 872-874, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000242.
[17] Zou Xingqi, Xia Zhiliang, Jin Lei, Zhang Yu, Jiang Dandan, Li Dong Hua, Xu Qiang, Hong Peizhen, Zeng Ming, Gao Jing, Tang Zhaoyun, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Simulation on Threshold Voltage of L-Shaped Bottom Select Transistor in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1122-1124, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000318.
[18] 孟令款, 洪培真, 贺晓彬, 李春龙, 李俊杰, 李俊峰, 赵超, 韦亚一, 闫江. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devicesLingkuan. Applied Surface Science[J]. 2016, http://159.226.55.106/handle/172511/16218.
[19] Meng, Lingkuan, Hong, Peizhen, He, Xiaobin, Li, Chunlong, Li, Junjie, Li, Junfeng, Zhao, Chao, Wei, Yayi, Yan, Jiang. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices. APPLIED SURFACE SCIENCE[J]. 2016, 362: 483-489, http://dx.doi.org/10.1016/j.apsusc.2015.11.139.
[20] Qin, Changliang, Wang, Guilei, Hong, Peizhen, Liu, Jinbiao, Yin, Huaxiang, Yin, Haizhou, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Xiang, Jinjuan, Zhong, Huicai, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Yan, Jian, Zhao, Chao, Radamson, Henry H. Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs. SOLID-STATE ELECTRONICS[J]. 2016, 123: 38-43, http://dx.doi.org/10.1016/j.sse.2016.05.017.
[21] Jiang Dandan, Xia Zhiliang, Jin Lei, Zhang Yu, Zou Xingqi, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Gao Jing, Zeng Ming, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Impact of Critical Geometry Dimension on Channel Boosting Potential in 3D NAND Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1248-1250, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000355.
[22] Zhang Yu, Jin Lei, Xia Zhiliang, Jiang Dandan, Zou Xingqi, Xu Qiang, Hong Peizhen, Tang Zhaoyun, Zeng Ming, Gao Jing, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. String Select Transistor Leakage Suppression by Threshold Voltage Modulation in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 872-874, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000242.
[23] Xu, Weijia, Yin, Huaxiang, Ma, Xiaolong, Hong, Peizhen, Xu, Miao, Meng, Lingkuan. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate. NANOSCALE RESEARCH LETTERS[J]. 2015, 10(1): http://www.irgrid.ac.cn/handle/1471x/1091060.
[24] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen, Xu, Weijia. Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-V-TH Operation on Si Substrate. ECS SOLID STATE LETTERS[J]. 2015, 4(4): Q13-Q16, http://www.irgrid.ac.cn/handle/1471x/1091061.
[25] Zhang, Yanbo, Zhu, Huilong, Wu, Hao, Zhang, Yongkui, Zhao, Zhiguo, Zhong, Jian, Yang, Hong, Liang, Qingqing, Wang, Dahai, Li, Junfeng, Jia, Cheng, Liu, Jinbiao, Zhao, Yuyin, Li, Chunlong, Meng, Lingkuan, Hong, Peizhen, Li, Junjie, Xu, Qiang, Gao, Jianfeng, He, Xiaobin, Lu, Yihong, Zhang, Yue, Yang, Tao, Wang, Yao, Cui, Hushan, Zhao, Chao, Yin, Huaxiang, Zhong, Huicai, Yin, Haizhou, Yan, Jiang, Wang, Wenwu, Chen, Dapeng, Yu, Hongyu, Yang, Simon, Ye, Tianchun. Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2015, 62(5): 1411-1418, http://www.irgrid.ac.cn/handle/1471x/1091057.
[26] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen. Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate. IEICE ELECTRONICS EXPRESS[J]. 2015, 12(7): http://10.10.10.126/handle/311049/15041.
[27] Li Xinkai, Huo Zongliang, Jin Lei, Jiang Dandan, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Li Chunlong, Ye Tianchun. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory. JOURNAL OF SEMICONDUCTORS[J]. 2015, 36(9): 94008-1, http://www.irgrid.ac.cn/handle/1471x/1089024.
[28] Xu, Weijia, Yin, Huaxiang, Ma, Xiaolong, Hong, Peizhen, Xu, Miao, Meng, Lingkuan. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate. NANOSCALE RESEARCH LETTERS[J]. 2015, 10(1): http://www.irgrid.ac.cn/handle/1471x/1091060.
[29] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen, Xu, Weijia. Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-V-TH Operation on Si Substrate. ECS SOLID STATE LETTERS[J]. 2015, 4(4): Q13-Q16, http://www.irgrid.ac.cn/handle/1471x/1091061.
[30] Zhang, Yanbo, Zhu, Huilong, Wu, Hao, Zhang, Yongkui, Zhao, Zhiguo, Zhong, Jian, Yang, Hong, Liang, Qingqing, Wang, Dahai, Li, Junfeng, Jia, Cheng, Liu, Jinbiao, Zhao, Yuyin, Li, Chunlong, Meng, Lingkuan, Hong, Peizhen, Li, Junjie, Xu, Qiang, Gao, Jianfeng, He, Xiaobin, Lu, Yihong, Zhang, Yue, Yang, Tao, Wang, Yao, Cui, Hushan, Zhao, Chao, Yin, Huaxiang, Zhong, Huicai, Yin, Haizhou, Yan, Jiang, Wang, Wenwu, Chen, Dapeng, Yu, Hongyu, Yang, Simon, Ye, Tianchun. Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2015, 62(5): 1411-1418, http://www.irgrid.ac.cn/handle/1471x/1091057.
[31] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen. Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate. IEICE ELECTRONICS EXPRESS[J]. 2015, 12(7): http://10.10.10.126/handle/311049/15041.
[32] Li Xinkai, Huo Zongliang, Jin Lei, Jiang Dandan, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Li Chunlong, Ye Tianchun. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory. JOURNAL OF SEMICONDUCTORS[J]. 2015, 36(9): 94008-1, http://www.irgrid.ac.cn/handle/1471x/1089024.
[33] Chen, Wenhui, Luo, Jun, Shi, Peixiong, Li, Chunlong, He, Xiaobin, Hong, Peizhen, Li, Junfeng, Zhao, Chao. Self-assembling morphologies of symmetrical PS-b-PMMA in different sized confining grooves. RSC ADVANCES[J]. 2014, 4(92): 50393-50400, http://dx.doi.org/10.1039/c4ra09573a.
[34] Zhao, Lichuan, Tang, Zhaoyun, Tang, Bo, Ma, Xueli, Liu, Jinbiao, Xiang, Jinjuan, Gao, Jianfeng, Li, Chunlong, He, Xiaobin, Jia, Cheng, Ding, Mingzheng, Yang, Hong, Xu, Yefeng, Xu, Jing, Wang, Hongli, Liu, Peng, Hong, Peizhen, Meng, Lingkuan, Li, Tingting, Xiong, Wenjuan, Wu, Hao, Li, Junjie, Wang, Guilei, Yang, Tao, Cui, Hushan, Lu, Yihong, Tong, Xiaodong, Luo, Jun, Zhong, Jian, Xu, Qiang, Wang, Wenwu, Li, Junfeng, Zhu, Huilong, Zhao, Chao, Yan, Jiang, Chen, Dapeng, Yang, Simon, Ye, Tianchun. Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs. IEEE ELECTRON DEVICE LETTERS[J]. 2014, 35(8): 811-813, http://dx.doi.org/10.1109/LED.2014.2331356.
[35] Meng, Lingkuan, He, Xiaobin, Li, Chunlong, Li, Junjie, Hong, Peizhen, Li, Junfeng, Zhao, Chao, Yan, Jiang. Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure. JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS[J]. 2014, 13(3): https://www.webofscience.com/wos/woscc/full-record/WOS:000342545000013.
[36] Chen, Wenhui, Luo, Jun, Shi, Peixiong, Li, Chunlong, He, Xiaobin, Hong, Peizhen, Li, Junfeng, Zhao, Chao. Self-assembling morphologies of symmetrical PS-b-PMMA in different sized confining grooves. RSC ADVANCES[J]. 2014, 4(92): 50393-50400, http://dx.doi.org/10.1039/c4ra09573a.
[37] Zhao, Lichuan, Tang, Zhaoyun, Tang, Bo, Ma, Xueli, Liu, Jinbiao, Xiang, Jinjuan, Gao, Jianfeng, Li, Chunlong, He, Xiaobin, Jia, Cheng, Ding, Mingzheng, Yang, Hong, Xu, Yefeng, Xu, Jing, Wang, Hongli, Liu, Peng, Hong, Peizhen, Meng, Lingkuan, Li, Tingting, Xiong, Wenjuan, Wu, Hao, Li, Junjie, Wang, Guilei, Yang, Tao, Cui, Hushan, Lu, Yihong, Tong, Xiaodong, Luo, Jun, Zhong, Jian, Xu, Qiang, Wang, Wenwu, Li, Junfeng, Zhu, Huilong, Zhao, Chao, Yan, Jiang, Chen, Dapeng, Yang, Simon, Ye, Tianchun. Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs. IEEE ELECTRON DEVICE LETTERS[J]. 2014, 35(8): 811-813, http://dx.doi.org/10.1109/LED.2014.2331356.
[38] Meng, Lingkuan, He, Xiaobin, Li, Chunlong, Li, Junjie, Hong, Peizhen, Li, Junfeng, Zhao, Chao, Yan, Jiang. Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure. JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS[J]. 2014, 13(3): https://www.webofscience.com/wos/woscc/full-record/WOS:000342545000013.
[5] 洪培真. 垂直沟道三维存储器控制栅阶梯工艺研究. 2020, [6] Hong, Peizhen, Zhao, Zhiguo, Luo, Jun, Xia, Zhiliang, Su, Xiaojing, Zhang, Libin, Li, Chunlong, Huo, Zongliang. An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND. IEEE ACCESS[J]. 2020, 8: 140054-140061, https://doaj.org/article/e9da23ff1a4543e3bc9c99f11603f5dc.
[7] Hong, Peizhen, Xia, Zhiliang, Yin, Huaxiang, Li, Chunlong, Huo, Zongliang. A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme). ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2019, 8(10): P567-P572, https://www.webofscience.com/wos/woscc/full-record/WOS:000488211700001.
[8] Hong, Peizhen, Xia, Zhiliang, Yin, Huaxiang, Li, Chunlong, Huo, Zongliang. A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme). ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2019, 8(10): P567-P572, https://www.webofscience.com/wos/woscc/full-record/WOS:000488211700001.
[9] Qin, Changliang, Yin, Huaxiang, Wang, Guilei, Hong, Peizhen, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Yin, Haizhou, Zhong, Huicai, Yan, Jiang, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Zhao, Chao, Radamson, Henry H. Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs. MICROELECTRONIC ENGINEERING[J]. 2017, 181: 22-28, http://dx.doi.org/10.1016/j.mee.2017.07.001.
[10] Qin, Changliang, Yin, Huaxiang, Wang, Guilei, Hong, Peizhen, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Yin, Haizhou, Zhong, Huicai, Yan, Jiang, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Zhao, Chao, Radamson, Henry H. Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs. MICROELECTRONIC ENGINEERING[J]. 2017, 181: 22-28, http://dx.doi.org/10.1016/j.mee.2017.07.001.
[11] Zou Xingqi, Xia Zhiliang, Jin Lei, Zhang Yu, Jiang Dandan, Li Dong Hua, Xu Qiang, Hong Peizhen, Zeng Ming, Gao Jing, Tang Zhaoyun, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Simulation on Threshold Voltage of L-Shaped Bottom Select Transistor in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1122-1124, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000318.
[12] 孟令款, 洪培真, 贺晓彬, 李春龙, 李俊杰, 李俊峰, 赵超, 韦亚一, 闫江. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devicesLingkuan. Applied Surface Science[J]. 2016, http://159.226.55.106/handle/172511/16218.
[13] Meng, Lingkuan, Hong, Peizhen, He, Xiaobin, Li, Chunlong, Li, Junjie, Li, Junfeng, Zhao, Chao, Wei, Yayi, Yan, Jiang. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices. APPLIED SURFACE SCIENCE[J]. 2016, 362: 483-489, http://dx.doi.org/10.1016/j.apsusc.2015.11.139.
[14] Qin, Changliang, Wang, Guilei, Hong, Peizhen, Liu, Jinbiao, Yin, Huaxiang, Yin, Haizhou, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Xiang, Jinjuan, Zhong, Huicai, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Yan, Jian, Zhao, Chao, Radamson, Henry H. Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs. SOLID-STATE ELECTRONICS[J]. 2016, 123: 38-43, http://dx.doi.org/10.1016/j.sse.2016.05.017.
[15] Jiang Dandan, Xia Zhiliang, Jin Lei, Zhang Yu, Zou Xingqi, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Gao Jing, Zeng Ming, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Impact of Critical Geometry Dimension on Channel Boosting Potential in 3D NAND Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1248-1250, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000355.
[16] Zhang Yu, Jin Lei, Xia Zhiliang, Jiang Dandan, Zou Xingqi, Xu Qiang, Hong Peizhen, Tang Zhaoyun, Zeng Ming, Gao Jing, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. String Select Transistor Leakage Suppression by Threshold Voltage Modulation in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 872-874, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000242.
[17] Zou Xingqi, Xia Zhiliang, Jin Lei, Zhang Yu, Jiang Dandan, Li Dong Hua, Xu Qiang, Hong Peizhen, Zeng Ming, Gao Jing, Tang Zhaoyun, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Simulation on Threshold Voltage of L-Shaped Bottom Select Transistor in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1122-1124, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000318.
[18] 孟令款, 洪培真, 贺晓彬, 李春龙, 李俊杰, 李俊峰, 赵超, 韦亚一, 闫江. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devicesLingkuan. Applied Surface Science[J]. 2016, http://159.226.55.106/handle/172511/16218.
[19] Meng, Lingkuan, Hong, Peizhen, He, Xiaobin, Li, Chunlong, Li, Junjie, Li, Junfeng, Zhao, Chao, Wei, Yayi, Yan, Jiang. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices. APPLIED SURFACE SCIENCE[J]. 2016, 362: 483-489, http://dx.doi.org/10.1016/j.apsusc.2015.11.139.
[20] Qin, Changliang, Wang, Guilei, Hong, Peizhen, Liu, Jinbiao, Yin, Huaxiang, Yin, Haizhou, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Xiang, Jinjuan, Zhong, Huicai, Zhu, Huilong, Xu, Qiuxia, Li, Junfeng, Yan, Jian, Zhao, Chao, Radamson, Henry H. Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs. SOLID-STATE ELECTRONICS[J]. 2016, 123: 38-43, http://dx.doi.org/10.1016/j.sse.2016.05.017.
[21] Jiang Dandan, Xia Zhiliang, Jin Lei, Zhang Yu, Zou Xingqi, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Gao Jing, Zeng Ming, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. Impact of Critical Geometry Dimension on Channel Boosting Potential in 3D NAND Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1248-1250, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000355.
[22] Zhang Yu, Jin Lei, Xia Zhiliang, Jiang Dandan, Zou Xingqi, Xu Qiang, Hong Peizhen, Tang Zhaoyun, Zeng Ming, Gao Jing, Mei Shaoning, Huo Zongliang, Jiang YL, Tang TA, Huang R. String Select Transistor Leakage Suppression by Threshold Voltage Modulation in 3D NAND Flash Memory. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 872-874, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000242.
[23] Xu, Weijia, Yin, Huaxiang, Ma, Xiaolong, Hong, Peizhen, Xu, Miao, Meng, Lingkuan. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate. NANOSCALE RESEARCH LETTERS[J]. 2015, 10(1): http://www.irgrid.ac.cn/handle/1471x/1091060.
[24] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen, Xu, Weijia. Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-V-TH Operation on Si Substrate. ECS SOLID STATE LETTERS[J]. 2015, 4(4): Q13-Q16, http://www.irgrid.ac.cn/handle/1471x/1091061.
[25] Zhang, Yanbo, Zhu, Huilong, Wu, Hao, Zhang, Yongkui, Zhao, Zhiguo, Zhong, Jian, Yang, Hong, Liang, Qingqing, Wang, Dahai, Li, Junfeng, Jia, Cheng, Liu, Jinbiao, Zhao, Yuyin, Li, Chunlong, Meng, Lingkuan, Hong, Peizhen, Li, Junjie, Xu, Qiang, Gao, Jianfeng, He, Xiaobin, Lu, Yihong, Zhang, Yue, Yang, Tao, Wang, Yao, Cui, Hushan, Zhao, Chao, Yin, Huaxiang, Zhong, Huicai, Yin, Haizhou, Yan, Jiang, Wang, Wenwu, Chen, Dapeng, Yu, Hongyu, Yang, Simon, Ye, Tianchun. Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2015, 62(5): 1411-1418, http://www.irgrid.ac.cn/handle/1471x/1091057.
[26] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen. Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate. IEICE ELECTRONICS EXPRESS[J]. 2015, 12(7): http://10.10.10.126/handle/311049/15041.
[27] Li Xinkai, Huo Zongliang, Jin Lei, Jiang Dandan, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Li Chunlong, Ye Tianchun. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory. JOURNAL OF SEMICONDUCTORS[J]. 2015, 36(9): 94008-1, http://www.irgrid.ac.cn/handle/1471x/1089024.
[28] Xu, Weijia, Yin, Huaxiang, Ma, Xiaolong, Hong, Peizhen, Xu, Miao, Meng, Lingkuan. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate. NANOSCALE RESEARCH LETTERS[J]. 2015, 10(1): http://www.irgrid.ac.cn/handle/1471x/1091060.
[29] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen, Xu, Weijia. Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-V-TH Operation on Si Substrate. ECS SOLID STATE LETTERS[J]. 2015, 4(4): Q13-Q16, http://www.irgrid.ac.cn/handle/1471x/1091061.
[30] Zhang, Yanbo, Zhu, Huilong, Wu, Hao, Zhang, Yongkui, Zhao, Zhiguo, Zhong, Jian, Yang, Hong, Liang, Qingqing, Wang, Dahai, Li, Junfeng, Jia, Cheng, Liu, Jinbiao, Zhao, Yuyin, Li, Chunlong, Meng, Lingkuan, Hong, Peizhen, Li, Junjie, Xu, Qiang, Gao, Jianfeng, He, Xiaobin, Lu, Yihong, Zhang, Yue, Yang, Tao, Wang, Yao, Cui, Hushan, Zhao, Chao, Yin, Huaxiang, Zhong, Huicai, Yin, Haizhou, Yan, Jiang, Wang, Wenwu, Chen, Dapeng, Yu, Hongyu, Yang, Simon, Ye, Tianchun. Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance. IEEE TRANSACTIONS ON ELECTRON DEVICES[J]. 2015, 62(5): 1411-1418, http://www.irgrid.ac.cn/handle/1471x/1091057.
[31] Ma, Xiaolong, Yin, Huaxiang, Hong, Peizhen. Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate. IEICE ELECTRONICS EXPRESS[J]. 2015, 12(7): http://10.10.10.126/handle/311049/15041.
[32] Li Xinkai, Huo Zongliang, Jin Lei, Jiang Dandan, Hong Peizhen, Xu Qiang, Tang Zhaoyun, Li Chunlong, Ye Tianchun. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory. JOURNAL OF SEMICONDUCTORS[J]. 2015, 36(9): 94008-1, http://www.irgrid.ac.cn/handle/1471x/1089024.
[33] Chen, Wenhui, Luo, Jun, Shi, Peixiong, Li, Chunlong, He, Xiaobin, Hong, Peizhen, Li, Junfeng, Zhao, Chao. Self-assembling morphologies of symmetrical PS-b-PMMA in different sized confining grooves. RSC ADVANCES[J]. 2014, 4(92): 50393-50400, http://dx.doi.org/10.1039/c4ra09573a.
[34] Zhao, Lichuan, Tang, Zhaoyun, Tang, Bo, Ma, Xueli, Liu, Jinbiao, Xiang, Jinjuan, Gao, Jianfeng, Li, Chunlong, He, Xiaobin, Jia, Cheng, Ding, Mingzheng, Yang, Hong, Xu, Yefeng, Xu, Jing, Wang, Hongli, Liu, Peng, Hong, Peizhen, Meng, Lingkuan, Li, Tingting, Xiong, Wenjuan, Wu, Hao, Li, Junjie, Wang, Guilei, Yang, Tao, Cui, Hushan, Lu, Yihong, Tong, Xiaodong, Luo, Jun, Zhong, Jian, Xu, Qiang, Wang, Wenwu, Li, Junfeng, Zhu, Huilong, Zhao, Chao, Yan, Jiang, Chen, Dapeng, Yang, Simon, Ye, Tianchun. Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs. IEEE ELECTRON DEVICE LETTERS[J]. 2014, 35(8): 811-813, http://dx.doi.org/10.1109/LED.2014.2331356.
[35] Meng, Lingkuan, He, Xiaobin, Li, Chunlong, Li, Junjie, Hong, Peizhen, Li, Junfeng, Zhao, Chao, Yan, Jiang. Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure. JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS[J]. 2014, 13(3): https://www.webofscience.com/wos/woscc/full-record/WOS:000342545000013.
[36] Chen, Wenhui, Luo, Jun, Shi, Peixiong, Li, Chunlong, He, Xiaobin, Hong, Peizhen, Li, Junfeng, Zhao, Chao. Self-assembling morphologies of symmetrical PS-b-PMMA in different sized confining grooves. RSC ADVANCES[J]. 2014, 4(92): 50393-50400, http://dx.doi.org/10.1039/c4ra09573a.
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科研活动
科研项目
（ 1 ） 中科院青促会项目, 主持, 研究所（学校）, 2019-01--2022-12