本课题组每年招收约1个博士生和1-2个硕士生（特别说明：不接受外单位调剂）。I do NOT accept any foreign students.

本课题组从事集成电路和体系结构设计方法学的前沿研究，研究成果落地于国产商业EDA软件和国产存算芯片，相关论文发表在CCF A类等高水平国际会议和期刊上。

我希望你是：

1.务实的人。简历、面试过程中不要强调获奖，尤其是参与人数众多的竞赛获奖（例如，数学建模、蓝桥杯）；应注重你做过的事情，能说清事情的逻辑（问题、解决思路、方法、效果、你的收获等）。

2.实事求是的人。准确地表达一个项目中你参与的部分；准确地表达你独创的工作和对已有工作的使用、借鉴；谨慎使用“熟练掌握”甚至“精通”这样的词。

3.出于兴趣而从事科研，自我驱动。

在本课题组读硕/博，我希望你在毕业时成为：

1.你所从事的研究方向的专家。在这个方向上比我做的更好，对该方向的发展历史、技术方法、前沿问题具有深入的认识。

2.知识面广的学者。在所从事的研究方向之外，也要有所了解，对于未知的问题能够找到合适的入手点，探索解决思路。

3.善于表达的科技工作者。能够以合理、严谨的方式宣传自己的工作。

2024. 《SCIENCE CHINA Information Sciences》2023年度热点论文奖/2023 Hot Paper Award of SCIENCE CHINA Information Sciences

2023. 中国科学院青年创新促进会优秀会员/Excellent Member of Youth Innovation Promotion Association CAS

2022. ASP-DAC 2022最佳论文奖/ASP-DAC 2022 Best Paper Award

2021. 获得国家自然科学基金-优青项目资助/NSFC Excellent Young Scientists Fund

2019. 入选北京智源人工智能研究院青年科学家/Young Scientist of BAAI

2019. 入选中国科学院青年创新促进会/Youth Innovation Promotion Association CAS

2018. 入选中国科协青年人才托举工程（全国<300人）/Young Elite Scientists Sponsorship Program by CAST

2018. 首届达摩院青橙奖（全国9人获奖）/Damo Academy Young Fellow Award

2016. 欧洲设计与自动化协会杰出博士论文奖（迄今中国大陆唯一获奖者）/2016 EDAA Outstanding Dissertation Award

2014. 清华大学优秀博士学位论文/Tsinghua University Outstanding PhD Dissertation Award

2014. 北京市优秀毕业生/Excellent Graduate of Beijing

2014. ASP-DAC 2014最佳论文提名奖/Best Paper Nomination, ASP-DAC 2014

2013. 国家奖学金/National Scholarship

2012. 教育部博士研究生学术新人奖

2012. ASP-DAC 2012最佳论文提名奖/Best Paper Nomination, ASP-DAC 2012

2009. ISLPED 2009最佳论文提名奖/Best Paper Nomination, ISLPED 2009

2009. 清华大学优秀本科毕设论文/Tsinghua University Outstanding Undergraduate Thesis Award

2005. 中国数学奥林匹克（全国决赛）二等奖，保送清华大学

2004. 全国高中数学联赛一等奖，入选江苏省队

张啸宇，中国教育发展基金会2023年“奋进奖学金-集成电路人才培养”项目（全国仅95人获奖）

孙晓天，国家奖学金

李泽润，国家奖学金

王新宇，国家奖学金

宋涛，国家奖学金

杨雨昕，国家奖学金

刘博生，国家奖学金

张啸宇，王守武奖学金（优秀奖）

张啸宇，中国科学院大学优秀毕业生 & 北京市优秀毕业生

刘博生，中国科学院大学优秀毕业生 & 北京市优秀毕业生

沈力博，所长优秀奖

宋涛，所长优秀奖

张啸宇，中国科学技术大学（校级）优秀毕业设计

李宛茜，南开大学（校级）优秀毕业设计

李宛茜，联想奖学金

李泽润，ASP-DAC 2022最佳论文奖

李泽润，易方达博士生奖

王新宇，易方达新生奖学金

刘博生，朱李月华奖

刘博生，华为博士生奖

徐晟，虑得博士生奖

2024/10-now, Institute of Computing Technology, Chinese Academy of Sciences

Professor

2017/11-2024/10, Institute of Computing Technology, Chinese Academy of Sciences

Associate Professor

2016/09-2017/10, University of Notre Dame

Full-Time Visiting Assistant Professor in Computer Science and Engineering. Work with Prof. X. Sharon Hu （胡晓波） and Prof. Danny Z. Chen （陈子仪）

2014/10-2016/08, Carnegie Mellon University

Postdoc Research Associate in Electrical and Computer Engineering. Work with Prof. Xin Li （李昕）

2009/08-2014/07, Tsinghua University

Ph.D. in Electronic Engineering, Advisors: Prof. Huazhong Yang and Prof. Yu Wang

2005/08-2009/07, Tsinghua University

B.S. in Electronic Engineering

I have published 130+ papers in top-tier conferences and journals, such as DAC, ICCAD, MICRO, HPCA, ASPLOS, IEEE TCAD, IEEE TPDS, IEEE TC, etc.

Google scholar for my full publication list

BOOKS

Xiaoming Chen, Yu Wang, Huazhong Yang, "Parallel Sparse Direct Solver for Integrated Circuit Simulation", Springer International Publishing, 1st edition, Feb. 2017. 136 pages.

SELECTED JOURNAL PAPERS

[TC] Zerun Li, Xiaoming Chen*, Feng Min, Xiaoyu Zhang, Yinhe Han, "A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing", IEEE Transactions on Computers (IEEE TC).

[TCAD] Xiaoming Chen, "CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

[TCAD] Xiaotian Sun, Xinyu Wang, Wanqian Li, Yinhe Han, Xiaoming Chen*, "PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

[TC] Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen*, Yinhe Han, “GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication”, IEEE Transactions on Computers (IEEE TC).

[TCAD] Rui Liu, Xiaoyu Zhang, Zhiwen Xie, Xinyu Wang, Zerun Li, Xiaoming Chen*, Yinhe Han, Minghua Tang. “FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-based In-memory Computing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

[TCAD] Xiaoyu Zhang, Rui Liu, Tao Song, Yuxin Yang, Yinhe Han, Xiaoming Chen*, "Re-FeMAT: A Reconfigurable Multifunctional FeFET-based Memory Architecture", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

[TCAD] Bosheng Liu, Xiaoming Chen*, Yinhe Han, Jigang Wu, Liang Chang, Peng Liu, Haobo Xu, "Search-free Inference Acceleration for Sparse Convolutional Neural Networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

[TCAD] Bosheng Liu, Xiaoming Chen*, Yinhe Han, Haobo Xu, "Swallow: A Versatile Accelerator for Sparse Neural Networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 38, no. 12, pp. 4881-4893, Dec 2020.

[TCAS-I] Xiaoming Chen, Kai Ni, Michael Niemier, Yinhe Han, Suman Datta, Xiaobo Sharon Hu, "Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs", IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE TCAS-I), vol. 66, no. 5, pp. 1780-1793, May 2019.

[TPDS] Xiaoming Chen, Danny Ziyi Chen, Yinhe Han, Xiaobo Sharon Hu, "moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units", IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), vol. 30, no. 3, pp. 646-661, March 2019.

[TCAD] Xiaoming Chen, Lin Wang, Boxun Li, Yu Wang, Xin Li, Yongpan Liu, Huazhong Yang, "Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol.35, no.9, pp.1435-1448, Sep. 2016.

[TPDS] Xiaoming Chen, Ling Ren, Yu Wang, Huazhong Yang, "GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling", IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), vol.26, no.3, pp.786-795, March 2015.

[TCAD] Xiaoming Chen, Yu Wang, Huazhong Yang, "NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol.32, no.2, pp.261-274, Feb. 2013.

SELECTED CONFERENCE PAPERS

[MICRO] Zerun Li, Xiaoming Chen*, Yinhe Han*, "TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining", in 2024 International Symposium on Microarchitecture (MICRO'24).

[ASPLOS] Xiaoyang Lu#, Boyu Long#, Xiaoming Chen*, Yinhe Han*, Xian-He Sun*, "ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations", in 2024 Architectural Support for Programming Languages and Operating Systems (ASPLOS'24).

[DAC] Ning Lin, Shaocong Wang, Yue Zhang, Yangu He, Kwunhang Wong, Arindam Basu, Dashan Shang, Xiaoming Chen*, Zhongrui Wang*, “Older and Wise: The Marriage of Device Aging and Intellectual Property Protection of DNNs”, in 2024 Design Automation Conference (DAC'24).

[DATE] Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen*, "PIMSYN: Synthesizing Processing-in-memory CNN Accelerators", in 2024 Design, Automation, and Test in Europe (DATE'24).

[MICRO] Yuxin Yang, Xiaoming Chen*, Yinhe Han, "DADU-RBD: Robot Rigid Body Dynamics Accelerator withMultifunctional Pipelines", in 56th IEEE/ACM International Symposium on Microarchitecture (MICRO'23).

[ICCAD] Libo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang, Yinhe Han, Xiaoming Chen*, "LIM-GEN: A Data-guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture", in International Conference on Computer-Aided Design (ICCAD'23).

[ICCAD] Boyu Long, Libo Shen, Xiaoyu Zhang, Yinhe Han, Xian-He Sun, Xiaoming Chen*, "Meltrix: A RRAM-based Polymorphic Architecture Enhanced by Function Synthesis", in International Conference on Computer-Aided Design (ICCAD'23).

[DAC] Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen*, Yinhe Han, “FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator”, in Design Automation Conference (DAC’23).

[DAC] Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen*, “PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators”, in Design Automation Conference (DAC’23).

[ICCAD] Xiaoming Chen, "Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit Simulation", in 2022 International Conference On Computer Aided Design (ICCAD’22). [acceptance rate: 132/586=22.5%]

[DAC] Zerun Li, Xiaoming Chen*, Yinhe Han, "GraphRing: an HMC-Ring based Graph Processing Framework with Optimized Data Movement", in 2022 Design Automation Conference (DAC'22).

[DAC] Tao Song, Xiaoming Chen*, Yinhe Han, "BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System", in 2021 Design Automation Conference (DAC'21).

[DAC] Yuxin Yang, Xiaoming Chen*, Yinhe Han, "Fast and Efficient Processing-in-Memory Accelerator for Collision Detection", in 2020 Design Automation Conference (DAC’20).

[HPCA] Xiaoming Chen, Yinhe Han, Yu Wang, "Communication Lower Bound in Convolution Accelerators", in 2020 International Symposium on High-Performance Computer Architecture (HPCA'20). [acceptance rate: 19.4%]

[ICCD] Xiaoyu Zhang, Xiaoming Chen*, Yinhe Han, "FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-based Memory Array", in 2019 37th International Conference on Computer Design (ICCD'19). [long, acceptance rate: 23.8%]

[DAC] Xiaoming Chen, Longxiang Yin, Bosheng Liu, Yinhe Han, "Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques", in 2019 56th Design Automation Conference (DAC'19).

[DATE] Xiaoming Chen, Danny Z. Chen, Xiaobo Sharon Hu, "moDNN: Memory Optimal DNN Training on GPUs", in 2018 21th Design, Automation, and Test in Europe (DATE'18). [long, acceptance rate: 23.7%]

[DATE] Xiaoming Chen, Xunzhao Yin, Michael Niemier, Xiaobo Sharon Hu, "Design and Optimization of FeFET-based Crossbars for Binary Convolution Neural Networks", in 2018 21th Design, Automation, and Test in Europe (DATE'18). [long, acceptance rate: 23.7%]

[DAC] Xiaoming Chen, Jianxu Chen, Danny Z. Chen, Xiaobo Sharon Hu, "Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs", in 2017 54th Design Automation Conference (DAC'17), pp.1-6, June 18-22, 2017. [acceptance rate: 160/676=23.7%]

[DATE] Xiaoming Chen, Lixue Xia, Yu Wang, Huazhong Yang, "Sparsity-Oriented Sparse Solver Design for Circuit Simulation", in 2016 19th Design, Automation, and Test in Europe (DATE'16), pp.1580-1585, March 14-18, 2016. [long, acceptance rate: 199/829=24%]

1. Parallel sparse linear solvers for SPICE simulators. Some techniques have been commercially adopted by a Chinese EDA company. The packages have been adopted by several world's leading institutes, universities, and companies. 

• NICSLU (mainly finished in Tsinghua University): parallel sparse direct solver for circuit simulation. NICSLU has been proven to be a high-performance solver in real circuit simulations by several leading EDA companies. https://github.com/chenxm1986/nicslu

• CKTSO: parallel sparse direct solver for circuit simulation. Successor of NICSLU. CKTSO has higher performance, better scalability and less memory usage than NICSLU. https://github.com/chenxm1986/cktso

• CKTSO-GPU: GPU acceleration module of CKTSO. https://github.com/chenxm1986/cktso-gpu

2. EDA tools for processing-in-memory architectures. Some techniques have been adopted by a Chinese IC company.

• PIM Toolchain: a suite of tools for PIM-based CNN accelerators, including PIMCOMP-NN, PIMSYN-NN, and PIMSIM-NN. https://github.com/chenxm1986/PIM-Toolchain

• PIMCOMP-NN: an NN compiler targeted at processing-in-memory architectures. It takes an ONNX file and an architecture configuration as inputs and produces an instruction stream, and during the compilation process, weight mapping and task scheduling are optimized. https://github.com/sunxt99/PIMCOMP-NN

• PIMSYN-NN: an architecture synthesizer targeted at processing-in-memory architectures. It takes an CNN structural description and some hardware constraints as inputs and generates an architecture together with dataflow scheduling. Design space exploration is performed during the synthesis process. https://github.com/lixixi-jook/PIMSYN-NN

• PIMSIM-NN: an NN simulator targeted at processing-in-memory architectures. It takes an instruction stream (produced by PIMCOMP-NN) and an architecture configuration as inputs and evaluates the performance (latency and/or throughput), power and energy of the NN running on the architecture. https://github.com/wangxy-2000/pimsim-nn

• PIMSIM: full-system simulator for near-data architectures, built based on GEM5. https://github.com/vineodd/PIMSim

3. Other tools.

• ChaoticWeights: a simple demonstration of using chaotic methods to protect the weights of a neural network running on an accelerator, for an [IEEE TCAD 2021] paper. https://github.com/chenxm1986/ChaoticWeights

Technical program committee member of DAC, ICCAD, ASP-DAC, GLSVLSI, CODES+ISSS, AsianHost, ISVLSI, etc.

Journal reviewer of Nature Communications, Scientific Reports, ACM JETC, ACM TODAES, ACM TCPS, IEEE TCAD, IEEE TC, IEEE TPDS, IEEE TCAS-I, IEEE TVLSI, IEEE TNNLS, IEEE JETCAS, etc.