专用硬件加速，FPGA可重构计算，容错计算

硕导

081201-计算机系统结构

专用芯片与系统设计，AI4EDA

2009-09--2016-04   香港大学   博士
2007-09--2009-07   哈尔滨工业大学   硕士
2003-09--2007-07   哈尔滨工业大学   本科

   

2018-06~现在, 中国科学院计算技术研究所, 副研
2016-12~2018-06,新加坡国立大学, Research Fellow

   

（1） 华为奥林帕斯奖, 一等奖, 其他, 2023

   

[1] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2024,   通讯作者  
[2] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2024,   通讯作者  
[3] 王梦迪, 王颖, 刘成, 常开颜, 高成思, 韩银和, 李华伟, 张磊. Puzzle：面向深度学习集成芯片的可扩展框架. 计算机研究与发展[J]. 2023, 第 3 作者60(6): 1216-1231, http://lib.cqvip.com/Qikan/Article/Detail?id=7109744548.
[4] 李雯, 王颖, 刘成, 何银涛, 刘炼, 李华伟, 李晓维. On-line Fault Protection for ReRAM-based Neural Networks. IEEE Transactions on Computers[J]. 2023, 第 3 作者72(2): 423-437, 
[5] Xue, Xinghua, 刘成, Wang, Ying, Yang, Bing, Luo, Tao, Zhang, Lei, Li, Huawei, Li, Xiaowei. Soft Error Reliability Analysis of Vision Transformers. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS[J]. 2023, 第 2 作者  通讯作者  null(null): http://dx.doi.org/10.1109/TVLSI.2023.3317138.
[6] 黄海同, 薛兴华, 刘成, 王颖, 李华伟, 李晓维. Statistical Modeling of Soft Error Influence on Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)[J]. 2023, 第 3 作者  通讯作者  
[7] Lv, Hao, Li, Bing, Zhang, Lei, Liu, Cheng, Wang, Ying. Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2023, 第 4 作者42(5): 1588-1596, http://dx.doi.org/10.1109/TCAD.2022.3207316.
[8] Erjing Luo, 黄海同, 刘成, 李国宇, Bing Yang, 王颖, 李华伟, 李晓维. DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. 2023 IEEE International Conference on Computer-Aided Design (ICCAD). 2023, 第 3 作者  通讯作者  null(null): 
[9] Li, Wen, Wang, Ying, Liu, Cheng, He, Yintao, Liu, Lian, Li, Huawei, Li, Xiaowei. On-Line Fault Protection for ReRAM-Based Neural Networks. IEEE TRANSACTIONS ON COMPUTERS[J]. 2023, 第 3 作者72(2): 423-437, http://dx.doi.org/10.1109/TC.2022.3160345.
[10] 褚诚, 刘成, 王颖, 李华伟, 李晓维. Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. ACM Transactions on Design Automation of Electronic Systems (TODAES)[J]. 2023, 第 2 作者  通讯作者  
[11] 薛兴华, 刘成, 刘波, 黄海同, 王颖, 罗涛, 张磊, 李华伟, 李晓维. Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)[J]. 2023, 第 2 作者  通讯作者  31(11): 1763-1773, 
[12] He, Yuquan, Zhang, Long, Liu, Cheng, Zhang, Lei, Wang, Ying. S-2 Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms. IEEE ROBOTICS AND AUTOMATION LETTERS[J]. 2023, 第 3 作者8(3): 1826-1833, http://dx.doi.org/10.1109/LRA.2023.3243809.
[13] Chen, Weiwei, Wang, Ying, Xu, Ying, Gao, Chengsi, Liu, Cheng, Zhang, Lei. A Framework for Neural Network Architecture and Compile Co-optimization. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS[J]. 2023, 第 5 作者22(1): 
[14] Liu, Cheng, Gao, Zhen, Liu, Siting, Ning, Xuefei, Li, Huawei, Li, Xiaowei. Fault-Tolerant Deep Learning: A Hierarchical Perspective. The 40th IEEE VLSI Test Symposium (VTS). 2022, 第 1 作者
[15] 何羽泉, 曲松云, 林刚亮, 王颖, 刘成, 张磊. Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception. In proceedings of ACM/IEEE Design Automation Conference (DAC). 2022, 第 5 作者
[16] Hui, Yajuan, Liu, Lei, Jiang, Hui, Wang, Kun, Liu, Cheng, Jin, Fang. Enhanced Output Performance in Spin-Valve Bridge Sensors by a Compound Nanostructure for Ferromagnetic Free Layers. JOURNAL OF ELECTRONIC MATERIALS[J]. 2022, 第 5 作者51(7): 3445-3452, http://dx.doi.org/10.1007/s11664-022-09629-0.
[17] Choong, Benjamin Chen Ming, Luo, Tao, Liu, Cheng, He, Bingsheng, Zhang, Wei, Zhou, Joey Tianyi. Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems. JOURNAL OF SYSTEMS ARCHITECTURE[J]. 2022, 第 3 作者128: http://dx.doi.org/10.1016/j.sysarc.2022.102507.
[18] Xue, Xinghua, Huang, Haitong, 刘成, Wang, Ying, Luo, Tao, Zhang, Lei. Winograd Convolution: A Perspective from Fault Tolerance. IN PROCEEDINGS OF ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC),. 2022, 第 3 作者  通讯作者  null(null): 
[19] 梁胜文, 袁梓铭, 王颖, 刘成, 李华伟, 李晓维. VStore: In-Storage Graph Based Vector Search Accelerator. ACM/IEEE Design Automation Conference (DAC). 2022, 第 4 作者
[20] 李福平, 王颖, 刘成, 李华伟, 李晓维. NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. Design, Automation & Test in Europe Conference. 2022, 第 3 作者
[21] Liang, Shengwen, Wang, Ying, Liu, Cheng, He, Lei, Li, Huawei, Xu, Dawen, Li, Xiaowei. （获得2021年最佳论文奖）EnGN： A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. IEEE TRANSACTIONS ON COMPUTERS[J]. 2021, 第 3 作者70(9): 1511-1525, 
[22] 何银涛, 王颖, 刘成, 李华伟, 李晓维. TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. In proceedings of ACM/IEEE Design Automation Conference (DAC). 2021, 第 3 作者
[23] 陈维伟, 王颖, 林刚亮, 高成思, 刘成, 张磊. CHaNAS: Coordinated Search for Network Architecture and Scheduling Policy. Language, Compilers, Tools and Theory of Embedded Systems (LCTES). 2021, 第 5 作者
[24] 刘成, Chu, Cheng, Xu, Dawen, Wang, Ying, Wang, Qianlong, Li, Huawei, Li, Xiaowei, Cheng, KwangTing. HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (TCAD)[J]. 2021, 第 1 作者null(null): http://arxiv.org/abs/2106.04772.
[25] 李沧元, 王颖, 刘成, 梁胜文, 李华伟, 李晓维. GLIST: Towards In-Storage Graph Learning. USENIX Annual Technical Conference (ATC). 2021, 第 3 作者  通讯作者  
[26] Xu, Dawen, Zhu, Ziyang, 刘成, Wang, Ying, Zhao, Shuang, Zhang, Lei, Liang, Huaguo, Li, Huawei, Cheng, KwangTing. Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS[J]. 2021, 第 3 作者  通讯作者  29(3): 472-484, http://dx.doi.org/10.1109/TVLSI.2020.3046075.
[27] Xu, Dawen, He, Meng, 刘成, Wang, Ying, Cheng, Long, Li, Huawei, Li, Xiaowei, Cheng, KwangTing. R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS[J]. 2021, 第 3 作者  通讯作者  29(11): 1955-1966, http://dx.doi.org/10.1109/TVLSI.2021.3089224.
[28] 王梦迪, 王颖, 刘成, 张磊. Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. proceedings of ACM/IEEE Design Automation Conference (DAC)[J]. 2021, 第 3 作者
[29] 马晓晗, 佀畅, 王颖, 刘成, 张磊. NASA: Accelerating Neural Network Design with a NAS Processor. International Symposium on Computer Architecture (ISCA)[J]. 2021, 第 4 作者
[30] 何羽泉, 王颖, 刘成, 张磊. PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices. The 2021 IEEE International Conference on Robotics and Automation (ICRA)[J]. 2021, 第 3 作者  通讯作者  
[31] Cheng, Long, Wang, Ying, Liu, Qingzhi, Epema, Dick H J, Liu, Cheng, Mao, Ying, Murphy, John. Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS[J]. 2021, 第 5 作者32(6): 1494-1510, http://dx.doi.org/10.1109/TPDS.2021.3053241.
[32] 贺磊, 刘成, 王颖, 梁胜文, 李华伟. GCiM: A Near-Data Processing Accelerator for Graph Construction. IEEE/ACM Proceedings of Design, Automation Conference (DAC). 2021, 第 2 作者
[33] Xu, Dawen, Liu, Cheng, Wang, Ying, Tu, Kaijie, He, Bingsheng, Zhang, Lei. Accelerating Generative Neural Networks on Unmodified Deep Learning Processors-A Software Approach. IEEE TRANSACTIONS ON COMPUTERS[J]. 2020, 第 2 作者69(8): 1172-1184, http://dx.doi.org/10.1109/TC.2020.3001033.
[34] 许达文, 王乾龙, 刘成, 褚程, 王颖, 梁华国, 郑光庭. A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators. The 38th IEEE International Conference on Computer Design (ICCD). 2020, 第 3 作者  通讯作者  
[35] 梁胜文, 刘成, 王颖, 李华伟, 李晓维. DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)[J]. 2020, 第 2 作者
[36] Zhao, Xiandong, Wang, Ying, Liu, Cheng, Shi, Cong, Tu, Kaijie, Zhang, Lei. BitPruner: Network Pruning for Bit-serial Accelerators. PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)[J]. 2020, 第 3 作者
[37] Xu, Dawen, Chu, Kexin, Liu, Cheng, Wang, Ying, Zhang, Lei, Li, Huawei. CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020)[J]. 2020, 第 3 作者  通讯作者  963-966, 
[38] Xu, Dawen, Zhu, Ziyang, Liu, Cheng, Wang, Ying, Li, Huawei, Zhang, Lei, Cheng, KwangTing. Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020)[J]. 2020, 第 3 作者  通讯作者  85-92, 
[39] Xu Dawen, Li Li, Wang Ying, Liu Cheng, Li Huawei. Exploring Emerging CNFET for Efficient Last Level Cache Design. 24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019)[J]. 2019, 第 4 作者426-431, http://dx.doi.org/10.1145/3287624.3287700.
[40] Liang Shengwen, Wang Ying, Liu Cheng, Li Huawei, Li Xiaowei. InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. 2019 29TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)[J]. 2019, 第 3 作者173-179, 
[41] 许达文, 邢扣子, 刘成, 王颖, 梁华国, 张磊. Resilient Neural Network Training for Accelerators with Computing Errors. The 30th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). 2019, 第 3 作者  通讯作者  
[42] Gui, ChuangYi, Zheng, Long, He, Bingsheng, Liu, Cheng, Chen, XinYu, Liao, XiaoFei, Jin, Hai. A Survey on Graph Processing Accelerators: Challenges and Opportunities. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY[J]. 2019, 第 4 作者34(2): 339-371, http://lib.cqvip.com/Qikan/Article/Detail?id=7001743641.
[43] 刘成, 陈鑫宇, 何丙胜, 王颖, 张磊. OBFS: OpenCL Based BFS Optimization on Software Programmable FPGAs. In 2019 International Conference on Field Programmable Technology (FPT). 2019, 第 1 作者  通讯作者  
[44] Xu Dawen, Tu Kaijie, Wang Ying, Liu Cheng, He Bingsheng, Li Huawei, Assoc Comp Machinery. FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors. 2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS. 2018, 第 4 作者
[45] Liu Cheng, Ng HoCheung, So Hayden KwokHay. QuickDough: A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay. 2015 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (FPT)[J]. 2015, 第 1 作者56-63, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000383741900008.
[46] Liu Cheng, Zhang Lei, Han Yinhe, Li Xiaowei, IEEE. Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip. 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 2011, 第 11 作者

（1） FPGA overlays. In FPGAs for Software Programmers, Springer, 2016-12, 第 2 作者
（2） Built-in Fault-tolerant Computing Paradigm for Resilient Large-Scale Chip Design, Springer Nature, 2023-05, 第 3 作者

   

（ 1 ） 基于FPGA的专用高能效图计算加速研究, 负责人, 国家任务, 2021-01--2022-12
（ 2 ） 面向深度学习处理器的弹性容错技术研究, 负责人, 国家任务, 2021-12--2025-12
（ 3 ） 容错深度学习处理器的自动化设计, 负责人, 研究所自主部署, 2021-06--2023-06
（ 4 ） 基于智能存算融合架构的大数据分析和调度框架, 负责人, 国家任务, 2023-01--2024-12
（ 5 ） 面向COTS器件的容错深度学习工具链研究, 负责人, 其他国际合作项目, 2023-01--2023-12
（ 6 ） 芯片设计跨层优化方法, 负责人, 国家任务, 2023-01--2025-12
（ 7 ） 面向处理器芯片跨层优化的软硬件平台, 负责人, 中国科学院计划, 2023-12--2028-12
（ 8 ） 面向遥感图像目标识别的智能微系统测评, 负责人, 境内委托项目, 2023-06--2024-06