人工智能加速器芯片设计；

计算机系统结构；

软硬件协同；

架构设计空间探索

2017-09--2019-09   杜克大学电子与计算机工程系   博士后
2010-09--2016-07   中国科学院大学   博士研究生

   

2024-11~现在, 中国科学院微电子研究所, 副研究员，青年研究员
2021-10~2022-11,中国科学院计算技术研究所国家重点实验室, 访问学者
2019-09~2024-11,首都师范大学, 副研究员

2025-03-31-今,计算机学会集成电路设计专委, 副秘书长
2025-03-01-2025-06-30,ICCAD, TPC member
2021-10-01-2024-01-30,DAC, TPC member

   

（1） Accelerating Unstructured Sparse DNNs via Multilevel Partial Sum Reduction and PE Array-Level Load Balancing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025, 第 4 作者
（2） High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data Mapping, Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025, 第 1 作者
（3） Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators, arxiv, 2025, 第 3 作者
（4） Attar:RRAM-based in-memory attention accelerator with software-hardware co-optimization, Attar: RRAM-based in-memory attention accelerator with software-hardware co-optimization, SCIENCE CHINA-INFORMATION SCIENCES, 2025, 第 1 作者  通讯作者
（5） UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architecture, 2025 IEEE International Symposium on High-Performance Computer Architecture, 2025, 第 3 作者
（6） Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM, arxiv, 2025, 第 3 作者
（7） Chiplever: Towards Effortless Extension of Chiplet-based System for Fully Homomorphic Encryption, 61st ACM/IEEE Design Automation Conference, 2024, 第 3 作者
（8） A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 第 2 作者  通讯作者
（9） CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators, PROCEEDINGS OF THE 29TH ACM INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS, ASPLOS 2024, VOL 2, 2024, 第 3 作者
（10） NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration, NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration, SCIENCE CHINA-INFORMATION SCIENCES, 2023, 第 3 作者  通讯作者
（11） A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 第 2 作者
（12） Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 第 2 作者
（13） An Automated Quantization Framework for High-Utilization RRAM-Based PIM, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 第 1 作者
（14） 3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks, ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2020, 第 1 作者  通讯作者
（15） RED: an ReRAM-based Efficient Accelerator for Deconvolutional Computation, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 第 1 作者
（16） RRAM based In-Memory Computing: From Device and Large-Scale Integration System Perspectives, Advanced Intelligent Systems, 2019, 第 2 作者

   

（ 1 ） 面向移动终端的忆阻器存内计算加速器设计方法和关键技术研究, 负责人, 国家任务, 2023-01--2025-12
（ 2 ） 类脑计算核心功能芯片电路设计, 参与, 国家任务, 2021-10--2025-10
（ 3 ） 低功耗芯片与系统, 参与, 国家任务, 2021-10--2025-10

（1）High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data Mapping   2025-01-20

现指导学生

李志举  硕士研究生  080902-电路与系统