张钊  男  研究员  博士生导师  中国科学院半导体研究所

电子邮件: zhangzhao11@semi.ac.cn
通信地址: 北京市海淀区清华东路35号甲中国科学院半导体研究所9号楼134
邮政编码:100083

个人主页(中国科学院大学):http://people.ucas.edu.cn/~ZhaoZhang_SEMI

个人主页(中国科学院半导体研究所):http://lab.semi.ac.cn/yanjiusheng/contents/1323/148623.html

研究领域与取得的代表性科研成果


研究领域

数模混合信号集成电路设计:

(1)CMOS高速通信集成电路设计;

(2)高性能时钟与本振源生成电路设计(PLL, CDR, DLL, 时钟分部等);

(3)面向生物传感的极低功耗集成电路设计。



取得的代表性科研成果

高性能时钟生成器集成电路设计

  1. 2017年研制出一款频率为18-23 GHz,RMS抖动小于60 fs,功耗13.7 mW的低功耗极低抖动锁相环时钟生成器,优值系数-253.5 dB,该项成果发表在电路与系统领域旗舰期刊IEEE Transactions on Circuits and Systems I: Regular Papers

  2. 2019年研制出一款能够在0.65-V电源电压下工作且RMS抖动小于60 fs的低功耗极低抖动抖动锁相环芯片,首次将小于60 fs的极低抖动锁相环的电源电压与功耗分别降低至0.7 V8 mW以内,该项成果分表在集成电路设计的顶级会议ISSCC 2019 (IEEE International Solid-State Circuits Conference)和顶级期刊JSSC 2020 (IEEE Journal of Solid-State Circuits)上。


用于数据中心的高速有线通信集成电路设计

  1. 2019分别研制出一款能效为 0.92 pJ/bit52-Gb/s PAM4 Receiver,在速率超过50 Gb/s前提下,能效首次优于1 pJ/bit,该项成果发表在集成电路设计顶级会议VLSI 2019 (2019 Symposia on VLSI Circuits)

  2. 2020年研制出能效和恢复时钟抖动分别小于0.5 pJ/bit360 fs的低功耗低抖动32-Gb/s PAM4 CDR,该项成果作发表在集成电路设计顶级期刊JSSC 2020 (IEEE Journal of Solid-State Circuits)上。

  3. 2021年研制出具有抖动补偿消除功能的60-Gb/s PAM4 Receiver,首次打破PAM4 CDR中抖动传递(JTRAN)和抖动容限(JTOL)之间的折中关系,能够在获得高JTOL的同时降低恢复时钟抖动60%,该项成果发表在集成电路设计顶级会议VLSI 2021上。


用于自供电传感器节点的极低电压极低功耗集成电路设计

  1. 2021年研制出一款0.15-1.6 GHz的极低电压极低功耗锁相环,首次将频率大于100MHz的锁相环的最低工作电压降低至0.25 V,且功耗首次降低至10 μW(@ 200 MHz)以下,能够较好满足自供电传感器节点SoC芯片的应用,该项成果发表在集成电路设计顶级期刊JSSC 2021 (IEEE Journal of Solid-State Circuits)上。


招生信息

每年计划招生1名博士,1~2名硕士。


招生专业
080902-电路与系统
招生方向
高性能数模混合集成电路设计
高速通信集成电路设计
面向生物传感的极低功耗集成电路设计

教育背景

2011-09--2016-07   中国科学院大学   博士
2007-09--2011-06   北京邮电大学   本科
学历
博士研究生

学位
工学博士

工作经历

   
工作简历
2022-02~现在, 中国科学院半导体研究所, 研究员
2020-11~2022-01,中国科学院半导体研究所, 副研究员
2019-04~2020-09,日本广岛大学, 助理教授
2019-03~2019-03,日本广岛大学, 博士后
2016-12~2018-12,香港科技大学, 博士后研究员
社会兼职
2020-10-21-今,国际会议2020 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2020), 分会主席
2018-06-28-今,国际会议IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 技术程序委员会(TPC)成员
2018-06-06-今,国际会议2018 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2018), 分会主席

教授课程

光电子集成芯片的高速电路设计

专利与奖励

   
专利成果
[1] 刘晓东, 吴南健, 王海永, 楼文峰, 陈晶晶, 张钊. 多标准性能可重构式I/Q正交载波发生器. CN: CN104079315B, 2018-09-04.

[2] Liu Xiaodong, Wu Nanjian, Wang Haiyong, Lou Wenfeng, Chen Jingjing, Zhang Zhao. MULTI-STANDARD PERFORMANCE RECONFIGURABLE I/Q ORTHOGONAL CARRIER GENERATOR. CN: US20170163270A1, 2017-06-08.

出版信息

   
发表论文
[1] Can Wang, Li Wang, 张钊, Milad Kalantari Mahmoudabadi, Weimin Shi, C Patrick Yue. A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. IEEE Open Journal of Circuits and Systems[J]. 2021, 2: 46-55, https://doaj.org/article/d785a78287db422c93edaa673164c15b.
[2] Tong Fan, Min Liu, Li-Yuan Liu, Zi-Teng Cai, Run-Jiang Dou, Peng Feng, Nan Qi, Zhao Zhang, Jian Liu, Nan-Jian Wu. A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. IEEE International Conference on Integrated Circuits, Technologies and Applicationsnull. 2021, [3] Meng, Xiangyu, Zheng, Zhenpeng, Li, Yecong, Zhang, Zhao. A K-Band Compact Power Divider/Combiner With 50-dB Configurable Isolation in 65-nm CMOS. IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS[J]. 2021, 31(8): 1001-1003, [4] Zhang, Zhao, Zhu, Guang, Yue, C Patrick. A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps. IEEE JOURNAL OF SOLID-STATE CIRCUITS[J]. 2021, 56(6): 1871-1885, http://dx.doi.org/10.1109/JSSC.2020.3028376.
[5] Li Wang, 张钊, C. Patrick Yue. A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery. 2021 Symposia on VLSI Circuits[J]. 2021, [6] Zhang, Zhao, Liu, Liyuan, Qi, Nan, Liu, Jian, Wu, Nanjian. A 17.6-to-24.3 GHz-193.3 dB figure-of-merit LC voltage-controlled oscillator using layout floorplan optimization technique for Q-factor enhancement. JAPANESE JOURNAL OF APPLIED PHYSICS[J]. 2020, 59: https://www.webofscience.com/wos/woscc/full-record/WOS:000519630000127.
[7] Zhang, Zhao, Zhu, Guang, Yue, C Patrick. A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fs(rms) Integrated Jitter and-256.4-dB FoM. IEEE JOURNAL OF SOLID-STATE CIRCUITS[J]. 2020, 55(6): 1665-1683, https://www.webofscience.com/wos/woscc/full-record/WOS:000538162500019.
[8] 张钊, Zhu, Guang, Wang, Can, Wang, Li, Yue, C Patrick. A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator. IEEE JOURNAL OF SOLID-STATE CIRCUITS[J]. 2020, 55(10): 2734-2746, https://www.webofscience.com/wos/woscc/full-record/WOS:000572629500011.
[9] Zhang Zhao. Design of High-Performance Phase-Locked Loop Using Hybrid Dual-Path Loop Architecture: an Overview (Invited Paper). 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2020). 2020, [10] Zhao Zhang. CMOS analog and mixed-signal phase-locked loops: An overview. 半导体学报:英文版null. 2020, 41(11): 13-30, http://lib.cqvip.com/Qikan/Article/Detail?id=7103228573.
[11] Hu, Junfeng, Zhang, Zhao, Pan, Quan. A 15-Gb/s 0.0037-mm(2) 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS[J]. 2020, 67(9): 1499-1503, https://www.webofscience.com/wos/woscc/full-record/WOS:000567210300003.
[12] 张钊. A 52-Gb/s Sub-1pJ /bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. 2019 Symposium on VLSI Circuits (VLSI 2019)[J]. 2019, [13] Di, Qian, Zhang, Zhongxing, Li, Honglong, Zhang, Zhao, Feng, Peng, Wu, Nanjian. Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. IEICE ELECTRONICS EXPRESS[J]. 2019, 16(21): [14] Zhang, Zhao, Yang, Jincheng, Liu, Liyuan, Qi, Nan, Feng, Peng, Liu, Jian, Wu, Nanjian. 0.1-5 GHz wideband Delta sigma fractional-N frequency synthesiser for software-defined radio application. IET CIRCUITS DEVICES & SYSTEMS[J]. 2019, 13(7): 1071-1077, [15] Zhang Zhao. A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps. 2019 Symposium on VLSI Circuits (VLSI 2019). 2019, [16] Cao Jing, Zhang Zhao, Qi Nan, Liu Liyuan, Wu Nanjian. A 16×1Pixels 180nm CMOS SPAD-based TOF Image Sensor for LiDAR Applications. Acta Photonica Sinica[J]. 2019, 48(7): [17] 张钊, Zhu Guang, Yue C Patrick. A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fs(rms) Integrated Jitter and-256.4dB FoM. 2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)[J]. 2019, 62: 488-+, [18] 张钊, Zhu, Guang, Wang, Can, Wang, Li, Yue, C Patrick. A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. 2019 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)[J]. 2019, 241-242, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000569524500068.
[19] Zhang, Zhao, Yang, Jincheng, Liu, Liyuan, Qi, Nan, Feng, Peng, Liu, Jian, Wu, Nanjian. An 18-23 GHz 57.4-fs RMS Jitter-253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL with Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS[J]. 2019, 66(10): 3733-3746, [20] Yang, Jincheng, Zhang, Zhao, Qi, Nan, Liu, Liyuan, Liu, Jian, Wu, Nanjian. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. SCIENCE CHINA-INFORMATION SCIENCES[J]. 2019, 62(6): http://lib.cqvip.com/Qikan/Article/Detail?id=74708871504849574854484948.
[21] Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, Nanjian Wu. A fast-locking bang-bang phase-locked loop with adaptive loop gain controller. JOURNAL OF SEMICONDUCTORS[J]. 2018, 39(12): 166-172, http://lib.cqvip.com/Qikan/Article/Detail?id=6100088692.
[22] Liao Qiwen, Qi Nan, Zhang Zhao, Liu Liyuan, Liu Jian, Wu Nanjian, Xiao Xi, Chiang Patrick Yin, IEEE. The Design Techniques for High-Speed PAM4 Clock and Data Recovery. PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, TECHNOLOGIES AND APPLICATIONS (ICTA 2018)null. 2018, 142-143, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000469280200062.
[23] Zhang Zhao. A 2-to-10 GHz 1.4-mW 50% Duty- Cycle Corrector in 40-nm CMOS Process (Invited Paper). 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC 2018). 2018, [24] Zhang, Zhao, Yang, Jincheng, Liu, Liyuan, Qi, Nan, Feng, Peng, Liu, Jian, Wu, Nanjian, IEEE. A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. 2018 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC): PROCEEDINGS OF TECHNICAL PAPERSnull. 2018, 227-230, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000459847500069.
[25] Yang, Jincheng, Zhang, Zhao, Qi, Nan, Liu, Liyuan, Liu, Jian, Wu, Nanjian. 2.4-3.2 GHz robust self-injecting injection-locked phase-locked loop. JAPANESE JOURNAL OF APPLIED PHYSICS[J]. 2018, 57(4): https://www.webofscience.com/wos/woscc/full-record/WOS:000430981800072.
[26] Zhang, Zhao, Yang, Jincheng, Liu, Liyuan, Feng, Peng, Liu, Jian, Wu, Nanjian. A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS[J]. 2018, 26(5): 933-944, https://www.webofscience.com/wos/woscc/full-record/WOS:000430968600012.
[27] Zhang Zhao, Yue C Patrick, IEEE. A 12.5-Gb/s 4.8-mW Full-Rate CDR with Low-Power Sample-and-Hold Linear Phase Detector. PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, TECHNOLOGIES AND APPLICATIONS (ICTA 2018)null. 2018, 96-97, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000469280200040.
[28] Zhang Zhao. A 2.4-to-3.6 GHz Wideband Subharmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique. IEEE Transactions on Very Large Scale Integration Systems (TVLSI). 2017, [29] Liu, Zhaoyang, Liu, Liyuan, Zhang, Zhao, Liu, Jian, Wu, Nanjian. Terahertz detector for imaging in 180-nm standard CMOS process. SCIENCE CHINA-INFORMATION SCIENCES[J]. 2017, 60(8): https://www.webofscience.com/wos/woscc/full-record/WOS:000396239500001.
[30] Zhang, Zhao, Yang, Jincheng, Liu, Liyuan, Feng, Peng, Liu, Jian, Wu, Nanjian, IEEE. A 18-to-23 GHz-253.5dB-FoM Sub-Harmonically Injection-Locked ADPLL with ILFD Aided Adaptive Injection Timing Alignment Technique. 2017 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)null. 2017, 249-252, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000426511300063.
[31] Zhaoyang LIU, Liyuan LIU, Zhao ZHANG, Jian LIU, Nanjian WU. Terahertz detector for imaging in 180-nm standard CMOS process. 中国科学 信息科学(英文版)[J]. 2017, https://www.webofscience.com/wos/woscc/full-record/WOS:000396239500001.
[32] Zhang, Zhao, Liu, Liyuan, Feng, Peng, Liu, Jian, Wu, Nanjian. Compact 0.3-to-1.125GHz self-biased phase-locked loop for system-on-chip clock generation in 0.18 mu m CMOS. JAPANESE JOURNAL OF APPLIED PHYSICS[J]. 2016, 55(4): https://www.webofscience.com/wos/woscc/full-record/WOS:000373929400070.
[33] Zhang, Zhao, Yang, Jincheng, Liu, Liyuan, Feng, Peng, Liu, Jian, Wu, Nanjian. Source-switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL. ELECTRONICS LETTERS[J]. 2016, 52(14): 1211-1212, https://www.webofscience.com/wos/woscc/full-record/WOS:000379846400012.
[34] Zhang Zhao, Yang Jincheng, Liu Liyuan, Feng Peng, Liu Jian, Wu Nanjian, Jiang YL, Tang TA, Huang R. A 0.1-to-5 GHz Wideband AL Fractional-N Frequency Synthesizer for Software -Defined Radio Application. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)null. 2016, 1570-1572, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000478951000453.
[35] Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu. A 0.1-to-5 GHz Wideband ΔΣ Fractional-N Frequency Synthesizer for Software-Defined Radio Application. 2016, http://kns.cnki.net/KCMS/detail/detail.aspx?QueryID=0&CurRec=1&recid=&FileName=IEEE201610001403&DbName=IPFDLAST2017&DbCode=IPFD&yx=&pr=&URLID=&bsm=.
[36] 张钊. 宽带低抖动锁相环时钟产生器研究与设计. 2016, http://ir.semi.ac.cn/handle/172111/27197.

科研活动

   
科研项目
( 1 ) 中科院半导体所“卓越青年学者”启动经费, 主持, 市地级, 2020-11--2023-12
( 2 ) 低电压低抖动宽频低功耗锁相环的关键技术研究, 主持, 国家级, 2022-01--2025-12
( 3 ) 中国科学院高层次人才引进计划经费, 主持, 部委级, 2022-01--2024-12
( 4 ) 用于数据中心的高速低功耗有线通信收发器集成电路的研究与实现, 主持, 省级, 2021-08--2023-08
参与会议
(1)Design of Ultra-Low-Voltage PLL and Low-Jitter Low-Power PAM4 CDR (特邀)   2021华人芯片设计技术研讨会 (ICAC 2021)   2021-05-21
(2)Design of High-Performance Phase-Locked Loop Using Hybrid Dual-Path Loop Architecture: an Overview (特邀)   2020 IEEE International Conference on Solid-State and Integrated Circuit Technology   2020-11-04
(3)A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM (特邀)   2020华人芯片设计技术研讨会 (ICAC 2020)   2020-06-09
(4)A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator   2019 IEEE Asian Solid-State Circuit Conference (A-SSCC 2019)   2019-11-06
(5)A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps   2019 Symposia on VLSI Circuits (VLSI 2019)   2019-06-12
(6)A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM   2019 IEEE International Solid-State Circuit Conference (ISSCC 2019)   2019-02-20
(7)A 12.5-Gb/s 4.8-mW Full-Rate CDR with Low-Power Sample-and-Hold Linear Phase Detector   2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2018)   2018-11-23
(8)A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range   2018 IEEE Asian Solid-State Circuit Conference (A-SSCC 2018)   2018-11-07
(9)A 2-to-10 GHz 1.4-mW 50% Duty-Cycle Corrector in 40-nm CMOS process (特邀)   2018 International Conference on Electron Devices and Solid-State Circuits (EDSSC 2018)   2018-06-07
(10)A 18-to-23 GHz -253.5dB-FoM Sub-Harmonically Injection-Locked ADPLL with ILFD Aided Adaptive Injection Timing Alignment Technique   2017 IEEE Asian Solid-State Circuit Conference (A-SSCC 2017)   2017-06-08
(11)A Novel 2.4-to-3.6 GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptively Aligned Injection Timing   2014 IEEE Asian Solid-State Circuit Conference (A-SSCC 2014)   2014-11-12