081201-计算机系统结构
0812Z1-信息安全
081203-计算机应用技术

面向安全的处理器芯片架构和设计方法
计算机系统平台安全技术
容错计算

2009-08--2014-05   新南威尔士大学   博士

   

2014-06~2023-02,新南威尔士大学, 博士后研究员

   

（1） MP-ORAM: A Novel ORAM Design for Multicore Processor Systems, IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2023, 第 3 作者
（2） SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation, 2022, 第 1 作者
（3） HWST128: complete memory safety accelerator on RISC-V with metadata compression, 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC), 2022, 通讯作者
（4） FaSe: fast selective flushing to mitigate contention-based cache timing attacks, 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC), 2022, 第 1 作者
（5） COPS: A complete oblivious processing system, MICROPROCESSORS AND MICROSYSTEMS, 2021, 第 3 作者
（6） SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V, 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC), 2021, 第 2 作者
（7） Hardware Trojan Mitigation in Pipelined MPSoCs, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2020, 第 3 作者
（8） A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units, 2020 33RD INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2020 19TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2020, 第 2 作者
（9） Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors, IEEE TRANSACTIONS ON COMPUTERS, 2017, 通讯作者
（10） Processor Design for Soft Errors: Challenges and State of the Art, ACM COMPUTING SURVEYS, 2016, 通讯作者
（11） RECORD: Reducing Register Traffic for Checkpointing in Embedded Processors, PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, 通讯作者
（12） ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA, 2015 28TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID), 2015, 第 2 作者
（13） Side Channel Attacks in Embedded Systems: A Tale of Hostilities and Deterrence, PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015), 2015, 第 4 作者
（14） ARCHER: Communication-based Predictive Architecture Selection for Application Specific Multiprocessor Systems-on-Chip, 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, 第 5 作者
（15） DHASER: Dynamic Heterogeneous Adaptation for Soft-Error Resiliency in ASIP-based Multi-core Systems, 2013 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2013, 通讯作者
（16） RASTER: Runtime Adaptive Spatial/Temporal Error Resiliency for Embedded Processors, 2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2013, 通讯作者
（17） CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors, 2013 Design Automation Test in Europe, 2013, 第 1 作者
（18） Fine-grained hardware/software methodology for process migration in MPSoCs, ICCAD 2012, 2012, 第 1 作者
（19） Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors, DATE 2012, 2012, 第 1 作者