基本信息
张青竹  男  硕导  中国科学院微电子研究所
电子邮件: zhangqingzhu@ime.ac.cn
通信地址: 北京市朝阳区北土城西路3号
邮政编码: 100029

招生信息

   
招生专业
080903-微电子学与固体电子学
招生方向
先进硅集成电路器件与集成技术,硅纳米线传感器
硅纳米线传感器

教育背景

2016-09--2020-06   北京有色金属研究总院   博士
2011-09--2014-06   贵州大学   硕士

工作经历

   
工作简历
2016-09~2020-06,北京有色金属研究总院, 博士
2014-07~现在, 中国科学院微电子研究所, 研究实习员、助理研究员、副研究员、研究员
2011-09~2014-06,贵州大学, 硕士
社会兼职
2023-01-01-今,Rare Metals, 青年编委
2022-03-01-今,中国科学院青年促进会北京分会, 委员
2018-01-01-2022-12-31,中国科学院青年促进会, 会员

出版信息

   
发表论文
(1) 巨磁阻抗传感器在生物检测领域的研究进展, Research Progress of Giant Magneto-Impedance Sensors in Biological Detection Field, 微纳电子技术, 2022, 第 4 作者
(2) 4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process, NANOMATERIALS, 2022, 第 7 作者
(3) Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2022, 第 2 作者
(4) Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 第 2 作者
(5) 超薄Hf_(0.5)Zr_(0.5)O_(2)铁电薄膜制备及在ETSOI器件应用研究, Fabrication of Ultra-Thin Hf_(0.5)Zr_(0.5)O_(2) Film and Its Application on ETSOI Devices, 稀有金属, 2022, 第 5 作者
(6) Experimental Investigation of Ultrathin Al2O3 Ex-Situ Interfacial Doping Strategy on Laminated HKMG Stacks via ALD, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 第 6 作者
(7) 巨磁阻抗传感器在生物检测领域的研究进展, Research Progress of Giant Magneto-Impedance Sensors in Biological Detection Field, 微纳电子技术, 2022, 第 4 作者
(8) 4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process, NANOMATERIALS, 2022, 第 7 作者
(9) Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2022, 第 2 作者
(10) Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 第 2 作者
(11) 超薄Hf_(0.5)Zr_(0.5)O_(2)铁电薄膜制备及在ETSOI器件应用研究, Fabrication of Ultra-Thin Hf_(0.5)Zr_(0.5)O_(2) Film and Its Application on ETSOI Devices, 稀有金属, 2022, 第 5 作者
(12) Experimental Investigation of Ultrathin Al2O3 Ex-Situ Interfacial Doping Strategy on Laminated HKMG Stacks via ALD, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 第 6 作者
(13) Geometric Variability Aware Quantum Potential based Quasi-ballistic Compact Model for Stacked 6 nm-Thick Silicon Nanosheet GAA-FETs, IEEE International Electron Devices Meeting (IEDM), 2021, 第 9 作者
(14) 克服FET生物传感器德拜屏蔽效应的研究进展, Research Progress on Overcoming Debye Screening Effect of BioFETs, 半导体技术, 2021, 第 7 作者
(15) Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices, NANOMATERIALS, 2021, 第 1 作者
(16) Recovery Behavior of Interface Traps After Negative Bias Temperature Instability Stress in p-FinFETs Featuring Fast Trap Characterization Technique, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 第 2 作者
(17) Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2021, 第 1 作者
(18) Influence of Applied Stress on the Ferroelectricity of Thin Zr-Doped HfO2 Films, APPLIED SCIENCES-BASEL, 2021, 第 2 作者
(19) Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs, NANOMATERIALS, 2021, 第 2 作者
(20) 硅纳米线传感器灵敏度研究进展, Research Progress in Sensitivity of Silicon Nanowire Sensors, 微纳电子技术, 2021, 第 4 作者
(21) Geometric Variability Aware Quantum Potential based Quasi-ballistic Compact Model for Stacked 6 nm-Thick Silicon Nanosheet GAA-FETs, IEEE International Electron Devices Meeting (IEDM), 2021, 第 9 作者
(22) 克服FET生物传感器德拜屏蔽效应的研究进展, Research Progress on Overcoming Debye Screening Effect of BioFETs, 半导体技术, 2021, 第 7 作者
(23) Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices, NANOMATERIALS, 2021, 第 1 作者
(24) Recovery Behavior of Interface Traps After Negative Bias Temperature Instability Stress in p-FinFETs Featuring Fast Trap Characterization Technique, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 第 2 作者
(25) Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2021, 第 1 作者
(26) Influence of Applied Stress on the Ferroelectricity of Thin Zr-Doped HfO2 Films, APPLIED SCIENCES-BASEL, 2021, 第 2 作者
(27) Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs, NANOMATERIALS, 2021, 第 2 作者
(28) 硅纳米线传感器灵敏度研究进展, Research Progress in Sensitivity of Silicon Nanowire Sensors, 微纳电子技术, 2021, 第 4 作者
(29) 离子敏感场效应晶体管传感器研究进展, Research Advancement in Ion-Sensitive Field Effect Transistor Sensors, 微电子学, 2020, 第 3 作者
(30) CVD法制备二维MoS_(2)的形貌调控研究, Controllable Growth and Morphology Evolution of 2D MoS_(2)via CVD Method, 稀有金属, 2020, 第 3 作者
(31) Design and Simulation of Steep-Slope Silicon Cold Source FETs With Effective Carrier Distribution Model, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 第 6 作者
(32) A Gd-doped HfO2 single film for a charge trapping memory device with a large memory window under a low voltage, RSC ADVANCES, 2020, 第 3 作者
(33) Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs, 2020 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2020, 第 2 作者
(34) Novel Insulator Isolated Si NW Sensors Fabricated using Bulk Substrate with Low-cost and High-quality, 6TH ANNUAL INTERNATIONAL WORKSHOP ON MATERIALS SCIENCE AND ENGINEERING, 2020, 第 1 作者
(35) Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications, NANOMATERIALS, 2020, 第 5 作者
(36) Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2020, 第 9 作者
(37) Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs, IEEE ELECTRON DEVICE LETTERS, 2020, 第 2 作者
(38) O-2 plasma treated biosensor for enhancing detection sensitivity of sulfadiazine in a high-K HfO2 coated silicon nanowire array, SENSORS AND ACTUATORS B-CHEMICAL, 2020, 通讯作者
(39) 考虑背栅偏置的FOI FinFET电流模型, Current Model of FOI FinFETs with Back-Gate Bias, 半导体技术, 2020, 第 8 作者
(40) Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors, NANOMATERIALS, 2020, 第 6 作者
(41) Fabrication technique of the Si0.5Ge0.5 Fin for the high mobility channel FinFET device, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 第 10 作者
(42) A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm, MATERIALS, 2020, 第 5 作者
(43) 离子敏感场效应晶体管传感器研究进展, Research Advancement in Ion-Sensitive Field Effect Transistor Sensors, 微电子学, 2020, 第 3 作者
(44) CVD法制备二维MoS_(2)的形貌调控研究, Controllable Growth and Morphology Evolution of 2D MoS_(2)via CVD Method, 稀有金属, 2020, 第 3 作者
(45) Design and Simulation of Steep-Slope Silicon Cold Source FETs With Effective Carrier Distribution Model, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 第 6 作者
(46) A Gd-doped HfO2 single film for a charge trapping memory device with a large memory window under a low voltage, RSC ADVANCES, 2020, 第 3 作者
(47) Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs, 2020 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2020, 第 2 作者
(48) Novel Insulator Isolated Si NW Sensors Fabricated using Bulk Substrate with Low-cost and High-quality, 6TH ANNUAL INTERNATIONAL WORKSHOP ON MATERIALS SCIENCE AND ENGINEERING, 2020, 第 1 作者
(49) Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications, NANOMATERIALS, 2020, 第 5 作者
(50) Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2020, 第 9 作者
(51) Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs, IEEE ELECTRON DEVICE LETTERS, 2020, 第 2 作者
(52) O-2 plasma treated biosensor for enhancing detection sensitivity of sulfadiazine in a high-K HfO2 coated silicon nanowire array, SENSORS AND ACTUATORS B-CHEMICAL, 2020, 通讯作者
(53) 考虑背栅偏置的FOI FinFET电流模型, Current Model of FOI FinFETs with Back-Gate Bias, 半导体技术, 2020, 第 8 作者
(54) Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors, NANOMATERIALS, 2020, 第 6 作者
(55) Fabrication technique of the Si0.5Ge0.5 Fin for the high mobility channel FinFET device, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 第 10 作者
(56) A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm, MATERIALS, 2020, 第 5 作者
(57) A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2019, 第 7 作者
(58) 应用于堆叠纳米线MOS器件的STI工艺优化研究, Optimization of Shallow Trench Isolation in Fabrication of Stacked Nanowire MOS Devices, 真空科学与技术学报, 2019, 第 2 作者
(59) High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2019, 第 4 作者
(60) Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2019, 第 5 作者
(61) Process optimization of the Si0.7Ge0.3 Fin Formation for the STI first scheme, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2019, 第 6 作者
(62) Comprehensive Investigation of Flat-band Voltage Modulation by High-K NPT for Advanced HKMG Technology, 2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2019, 第 4 作者
(63) FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2, IEEE ELECTRON DEVICE LETTERS, 2019, 通讯作者
(64) Miniaturization of CMOS, MICROMACHINES, 2019, 第 3 作者
(65) Near-ideal subthreshold swing MoS2 back-gate transistors with an optimized ultrathin HfO2 dielectric layer, NANOTECHNOLOGY, 2019, 第 8 作者
(66) A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2019, 第 7 作者
(67) 应用于堆叠纳米线MOS器件的STI工艺优化研究, Optimization of Shallow Trench Isolation in Fabrication of Stacked Nanowire MOS Devices, 真空科学与技术学报, 2019, 第 2 作者
(68) High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2019, 第 4 作者
(69) Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2019, 第 5 作者
(70) Process optimization of the Si0.7Ge0.3 Fin Formation for the STI first scheme, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2019, 第 6 作者
(71) Comprehensive Investigation of Flat-band Voltage Modulation by High-K NPT for Advanced HKMG Technology, 2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2019, 第 4 作者
(72) FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2, IEEE ELECTRON DEVICE LETTERS, 2019, 通讯作者
(73) Miniaturization of CMOS, MICROMACHINES, 2019, 第 3 作者
(74) Near-ideal subthreshold swing MoS2 back-gate transistors with an optimized ultrathin HfO2 dielectric layer, NANOTECHNOLOGY, 2019, 第 8 作者
(75) Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si-0.45, Ge-0.55, Ge Gate-All-Around NSFET for 5nm Technology Node, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 第 5 作者
(76) Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel, Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel, CHINESE PHYSICS LETTERS, 2018, 第 4 作者
(77) 面向5 nm CMOS技术代堆叠纳米线释放工艺研究, Release of Stacked Nanowires for 5 nm CMOS Node: An Experimental Study, 真空科学与技术学报, 2018, 第 2 作者
(78) Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 4 作者
(79) First observation of Pt3Si phase at Ni(0.86)Ptod(4) and Si Silicide Reactions, 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, 第 1 作者
(80) Comparative Investigation of Flat-Band Voltage Modulation by Nitrogen Plasma Treatment for Advanced HKMG Technology, ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2018, 第 5 作者
(81) Total Ionizing Dose Response and Annealing Behavior of Bulk nFinFETs With ON-State Bias Irradiation, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2018, 第 2 作者
(82) Si Nanowire Biosensors Using a FinFET Fabrication Process for Real Time Monitoring Cellular Ion Actitivies, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 1 作者
(83) Influence of the hard masks profiles on formation of nanometer Si scalloped fins arrays, MICROELECTRONIC ENGINEERING, 2018, 通讯作者
(84) Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si-0.45, Ge-0.55, Ge Gate-All-Around NSFET for 5nm Technology Node, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 第 5 作者
(85) Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel, Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel, CHINESE PHYSICS LETTERS, 2018, 第 4 作者
(86) 面向5 nm CMOS技术代堆叠纳米线释放工艺研究, Release of Stacked Nanowires for 5 nm CMOS Node: An Experimental Study, 真空科学与技术学报, 2018, 第 2 作者
(87) Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 4 作者
(88) First observation of Pt3Si phase at Ni(0.86)Ptod(4) and Si Silicide Reactions, 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, 第 1 作者
(89) Comparative Investigation of Flat-Band Voltage Modulation by Nitrogen Plasma Treatment for Advanced HKMG Technology, ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2018, 第 5 作者
(90) Total Ionizing Dose Response and Annealing Behavior of Bulk nFinFETs With ON-State Bias Irradiation, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2018, 第 2 作者
(91) Si Nanowire Biosensors Using a FinFET Fabrication Process for Real Time Monitoring Cellular Ion Actitivies, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 1 作者
(92) Influence of the hard masks profiles on formation of nanometer Si scalloped fins arrays, MICROELECTRONIC ENGINEERING, 2018, 通讯作者
(93) Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure, ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2017, 第 2 作者
(94) Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-kappa Dielectrics and SiGe Epitaxial Substrates, CHINESE PHYSICS LETTERS, 2017, 第 6 作者
(95) Two methods of tuning threshold voltage of bulk FinFETs with replacement high-k metal-gate stacks, SOLID-STATE ELECTRONICS, 2017, 第 7 作者
(96) Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure, ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2017, 第 2 作者
(97) Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-kappa Dielectrics and SiGe Epitaxial Substrates, CHINESE PHYSICS LETTERS, 2017, 第 6 作者
(98) Two methods of tuning threshold voltage of bulk FinFETs with replacement high-k metal-gate stacks, SOLID-STATE ELECTRONICS, 2017, 第 7 作者
(99) 小尺寸器件的金属栅平坦化新技术, 真空科学与技术学报, 2016, 第 6 作者
(100) 小尺寸器件的金属栅平坦化新技术, 真空科学与技术学报, 2016, 第 6 作者
(101) Ni_u Pt_(1-u)Si_v Ge_(1-v)/ Si_(0.72)Ge_(0.28)界面形貌的改善, Improvement of the Interfacial Morphology of Ni_uPt_(1-u)Si_vGe_(1-v)/ Si_(0.72)Ge_(0.28), 半导体技术, 2015, 第 2 作者
(102) Niu Pt1 - u Siv Ge1 - v /Si0. 72 Ge0. 28界面形貌的改善, 半导体制造技术, 2015, 第 2 作者
(103) Ni_u Pt_(1-u)Si_v Ge_(1-v)/ Si_(0.72)Ge_(0.28)界面形貌的改善, Improvement of the Interfacial Morphology of Ni_uPt_(1-u)Si_vGe_(1-v)/ Si_(0.72)Ge_(0.28), 半导体技术, 2015, 第 2 作者
(104) Niu Pt1 - u Siv Ge1 - v /Si0. 72 Ge0. 28界面形貌的改善, 半导体制造技术, 2015, 第 2 作者
(105) 超薄Ni0.86Pt0.14金属硅化物薄膜特性, 半导体技术, 2014, 第 1 作者
(106) 超薄Ni0.86Pt0.14金属硅化物薄膜特性, 半导体技术, 2014, 第 1 作者

科研活动

   
科研项目
( 1 ) CMOS器件与集成技术, 负责人, 中国科学院计划, 2022-11--2025-10
( 2 ) 5 nm节点以下超薄铪基负电容材料稀土改性和三维架构协同效应研究, 负责人, 国家任务, 2020-01--2022-12
( 3 ) 硅纳米线xxx, 负责人, 其他国际合作项目, 2022-10--2025-09
( 4 ) 多栅负电容 MOS 器件和关键材料研究, 负责人, 地方任务, 2020-09--2023-08
参与会议
(1)Record 7(N)+7(P) Multiple V T s Demonstration on GAA Si Nanosheet n/pFETs using WFM-Less Direct Interfacial La/Al-Dipole Technique   姚佳欣   2022-12-03
(2)FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin   张青竹   2020-12-03
(3)Si Nanowire Biosensors Using a FinFET Fabrication Process for Real Time Monitoring Cellular Ion Actitivies   2018-12-03