基本信息
许晓欣 女 中国科学院微电子研究所
电子邮件: xuxiaoxin@ime.ac.cn
通信地址: 北京市朝阳区北土城西路三号
邮政编码:
电子邮件: xuxiaoxin@ime.ac.cn
通信地址: 北京市朝阳区北土城西路三号
邮政编码:
招生信息
招生专业
080903-微电子学与固体电子学080901-物理电子学085400-电子信息
招生方向
新型存储器,神经网络计算半导体器件可靠性新型存储器应用
教育背景
2014-09--2017-06 中国科学院大学 博士研究生2011-09--2014-06 山东大学 硕士研究生2007-09--2011-06 中国矿业大学 学士
工作经历
工作简历
2022-11~现在, 中科院微电子研究所, 研究员2020-07~2022-11,中科院微电子研究所, 副研究员2017-07~2020-07,中科院微电子研究所, 助理研究员
社会兼职
2022-06-01-2026-06-01,International memory workshop, TPC member,
2022-03-01-今,MDPI Micromachines Guest editor, Guest editor
2022-03-01-今,MDPI Micromachines Guest editor, Guest editor
专利与奖励
奖励信息
(1) 中科院青促会优秀会员, 院级, 2022(2) 华为奥林帕斯先锋奖, , 其他, 2021(3) 中科院微电子所先进个人, , 研究所(学校), 2021(4) 中科院杰出科技成就奖, 特等奖, 省级, 2018
专利成果
( 1 ) 一种忆阻器及其制作方法, 发明专利, 2022, 第 1 作者, 专利号: CN114242889A( 2 ) 一种忆阻器及其制作方法, 发明专利, 2022, 第 1 作者, 专利号: CN114242889A( 3 ) 忆阻器、制备方法及全忆阻器基的神经形态计算芯片, 发明专利, 2021, 第 1 作者, 专利号: CN113517391A( 4 ) 忆阻器、制备方法及全忆阻器基的神经形态计算芯片, 发明专利, 2021, 第 1 作者, 专利号: CN113517391A( 5 ) 基于磁畴壁驱动型磁隧道结的激活函数发生器及制备方法, 发明专利, 2021, 第 6 作者, 专利号: CN113193110A( 6 ) 基于磁畴壁驱动型磁隧道结的激活函数发生器及制备方法, 发明专利, 2021, 第 6 作者, 专利号: CN113193110A( 7 ) 一种阻变存储器及其制作方法, 发明专利, 2021, 第 1 作者, 专利号: CN112864318A( 8 ) 一种阻变存储器及其制作方法, 发明专利, 2021, 第 1 作者, 专利号: CN112864318A( 9 ) 阻变存储器、存算器件、芯片及阻变存储器的制备方法, 发明专利, 2021, 第 1 作者, 专利号: CN112838161A( 10 ) 阻变存储器、存算器件、芯片及阻变存储器的制备方法, 发明专利, 2021, 第 1 作者, 专利号: CN112838161A( 11 ) 一种阻变存储器预处理方法及装置, 发明专利, 2021, 第 2 作者, 专利号: CN112837732A( 12 ) 一种阻变存储器预处理方法及装置, 发明专利, 2021, 第 2 作者, 专利号: CN112837732A( 13 ) 神经网络计算电路、芯片及系统, 发明专利, 2021, 第 2 作者, 专利号: CN112580790A( 14 ) 神经网络计算电路、芯片及系统, 发明专利, 2021, 第 2 作者, 专利号: CN112580790A( 15 ) 存储单元结构及存储器阵列结构、电压偏置方法, 发明专利, 2020, 第 3 作者, 专利号: CN111446271A( 16 ) 存储单元结构及存储器阵列结构、电压偏置方法, 发明专利, 2020, 第 3 作者, 专利号: CN111446271A( 17 ) 融合型存储器的写入、擦除方法, 专利授权, 2019, 第 3 作者, 专利号: CN109887532A( 18 ) 融合型存储器的写入、擦除方法, 专利授权, 2019, 第 3 作者, 专利号: CN109887532A( 19 ) 融合型存储器, 专利授权, 2019, 第 3 作者, 专利号: CN109860190A( 20 ) 融合型存储器, 专利授权, 2019, 第 3 作者, 专利号: CN109860190A( 21 ) 神经网络运算系统, 发明专利, 2019, 第 2 作者, 专利号: CN109829540A( 22 ) 神经网络运算系统, 发明专利, 2019, 第 2 作者, 专利号: CN109829540A( 23 ) 存储器, 实用新型, 2019, 第 3 作者, 专利号: CN109801977A( 24 ) 存储器, 实用新型, 2019, 第 3 作者, 专利号: CN109801977A( 25 ) 1S1R存储器集成结构及其制备方法, 发明专利, 2018, 第 4 作者, 专利号: CN108630810A( 26 ) 1S1R存储器集成结构及其制备方法, 发明专利, 2018, 第 4 作者, 专利号: CN108630810A( 27 ) 一种阻变存储器的制造方法和阻变存储器, 专利授权, 2017, 第 3 作者, 专利号: CN107275482A( 28 ) 一种阻变存储器的制造方法和阻变存储器, 专利授权, 2017, 第 3 作者, 专利号: CN107275482A( 29 ) 一种提高RRAM均一性的方法及RRAM器件, 发明专利, 2017, 第 3 作者, 专利号: CN107221598A( 30 ) 一种提高RRAM均一性的方法及RRAM器件, 发明专利, 2017, 第 3 作者, 专利号: CN107221598A( 31 ) 用于双极性阻变存储器的选择器件及其制备方法, 专利授权, 2017, 第 3 作者, 专利号: CN107204397A( 32 ) 用于双极性阻变存储器的选择器件及其制备方法, 专利授权, 2017, 第 3 作者, 专利号: CN107204397A( 33 ) 基于过渡金属氧化物的选择器及其制备方法, 发明专利, 2017, 第 3 作者, 专利号: CN106910759A( 34 ) 基于过渡金属氧化物的选择器及其制备方法, 发明专利, 2017, 第 3 作者, 专利号: CN106910759A( 35 ) 基于两端器件的脉冲参数测试系统, 发明专利, 2016, 第 3 作者, 专利号: CN105957558A( 36 ) 基于两端器件的脉冲参数测试系统, 发明专利, 2016, 第 3 作者, 专利号: CN105957558A( 37 ) 一种自选通阻变存储器件及其制备方法, 发明专利, 2016, 第 3 作者, 专利号: CN105826468A( 38 ) 一种自选通阻变存储器件及其制备方法, 发明专利, 2016, 第 3 作者, 专利号: CN105826468A( 39 ) 一种有效提高阻变存储器耐久性的方法, 发明专利, 2015, 第 7 作者, 专利号: CN104464801A( 40 ) 一种有效提高阻变存储器耐久性的方法, 发明专利, 2015, 第 7 作者, 专利号: CN104464801A( 41 ) 对RRAM存储器耐久性参数进行测试的方法, 发明专利, 2014, 第 5 作者, 专利号: CN104134468A( 42 ) 对RRAM存储器耐久性参数进行测试的方法, 发明专利, 2014, 第 5 作者, 专利号: CN104134468A( 43 ) 一种对RRAM存储器保持时间参数进行测试的方法, 发明专利, 2014, 第 5 作者, 专利号: CN104134463A( 44 ) 一种对RRAM存储器保持时间参数进行测试的方法, 发明专利, 2014, 第 5 作者, 专利号: CN104134463A( 45 ) 一种降低阻变存储器电铸电压的方法, 发明专利, 2014, 第 6 作者, 专利号: CN103956428A( 46 ) 一种降低阻变存储器电铸电压的方法, 发明专利, 2014, 第 6 作者, 专利号: CN103956428A( 47 ) 一种对RRAM器件的脉冲参数进行测试的电路, 发明专利, 2014, 第 6 作者, 专利号: CN103531250A( 48 ) 一种对RRAM器件的脉冲参数进行测试的电路, 发明专利, 2014, 第 6 作者, 专利号: CN103531250A( 49 ) 一种制备纳米器件的方法, 发明专利, 2014, 第 6 作者, 专利号: CN103500701A( 50 ) 一种制备纳米器件的方法, 发明专利, 2014, 第 6 作者, 专利号: CN103500701A
出版信息
发表论文
(1) Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array, MICROMACHINES, 2022, 第11作者(2) A Computing-in-memory macro with three-dimensional random-access memory, Nature Electronics, 2022, 第 2 作者(3) Effect of Bit Line Voltage Stress on Half-Selected Device in 1T1R Array, 2022 IEEE Silicon Nanoelectronics Workshop, 2022, 通讯作者(4) 3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm2) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing, IEEE Symposium on VLSI Technology, 2022, 通讯作者(5) Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array, MICROMACHINES, 2022, 第11作者(6) A Computing-in-memory macro with three-dimensional random-access memory, Nature Electronics, 2022, 第 2 作者(7) Effect of Bit Line Voltage Stress on Half-Selected Device in 1T1R Array, 2022 IEEE Silicon Nanoelectronics Workshop, 2022, 通讯作者(8) 3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm2) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing, IEEE Symposium on VLSI Technology, 2022, 通讯作者(9) A 128kb Stochastic Computing Chip based on RRAM Flicker Noise with High Noise Density and Nearly Zero Autocorrelation on 28-nm CMOS Platform, 2021 IEEE International Electron Devices Meeting (IEDM), 2021, 第 6 作者(10) Quantitative Analysis on Resistance Fluctuation of Resistive Random Access Memory by Low Frequency Noise Measurement, IEEE ELECTRON DEVICE LETTERS, 2021, 第 4 作者(11) Resistive switching memory for high density storage and computing, Resistive switching memory for high density storage and computing*, CHINESE PHYSICS B, 2021, 第 1 作者(12) A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme, IEEE Symposium on VLSI Technology, 2021, 第 1 作者(13) 一种忆阻器阵列的阻值调制测试系统, A resistance modulation test system of memristor array, 微纳电子与智能制造, 2021, 第 4 作者(14) Effect of conductive filament morphology on soft error of oxide based Resistive Random Access Memory, 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2021, 通讯作者(15) Enabling RRAM-Based Brain-Inspired Computation by Co-design of Device, Circuit, and System, IEDM, 2021, 第 2 作者(16) Scaling Potential Analysis for the CMOS Compatible Ox-RRAM, 2021 IEEE International Memory Workshop (IMW), 2021, 第 1 作者(17) Efficient and Robust Nonvolatile Computing-In-Memory based on Voltage Division in 2T2R RRAM with Input-Dependent Sensing Control, IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 第 5 作者(18) A 14 nm 100Kb 2T2R transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme, IEEE Symposium on VLSI Technology, 2021, 第 9 作者(19) A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes, Symposium on VLSI Technology,, 2021, 第 5 作者(20) Energy efficient and robust reservoir computing system using ultrathin (3.5 nm) ferroelectric tunneling junctions for temporal data learning, IEEE Symposium on VLSI Technology, 2021, 通讯作者(21) Reliability Issues of Half-Selected Cells in Resistive Random Access Memory Array Integrated with 14nm FinFET, 2021 SILICON NANOELECTRONICS WORKSHOP (SNW), 2021, 通讯作者(22) A 128kb Stochastic Computing Chip based on RRAM Flicker Noise with High Noise Density and Nearly Zero Autocorrelation on 28-nm CMOS Platform, 2021 IEEE International Electron Devices Meeting (IEDM), 2021, 第 6 作者(23) Quantitative Analysis on Resistance Fluctuation of Resistive Random Access Memory by Low Frequency Noise Measurement, IEEE ELECTRON DEVICE LETTERS, 2021, 第 4 作者(24) Resistive switching memory for high density storage and computing, Resistive switching memory for high density storage and computing*, CHINESE PHYSICS B, 2021, 第 1 作者(25) A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme, IEEE Symposium on VLSI Technology, 2021, 第 1 作者(26) 一种忆阻器阵列的阻值调制测试系统, A resistance modulation test system of memristor array, 微纳电子与智能制造, 2021, 第 4 作者(27) Effect of conductive filament morphology on soft error of oxide based Resistive Random Access Memory, 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2021, 通讯作者(28) Enabling RRAM-Based Brain-Inspired Computation by Co-design of Device, Circuit, and System, IEDM, 2021, 第 2 作者(29) Scaling Potential Analysis for the CMOS Compatible Ox-RRAM, 2021 IEEE International Memory Workshop (IMW), 2021, 第 1 作者(30) Efficient and Robust Nonvolatile Computing-In-Memory based on Voltage Division in 2T2R RRAM with Input-Dependent Sensing Control, IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 第 5 作者(31) A 14 nm 100Kb 2T2R transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme, IEEE Symposium on VLSI Technology, 2021, 第 9 作者(32) A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes, Symposium on VLSI Technology,, 2021, 第 5 作者(33) Energy efficient and robust reservoir computing system using ultrathin (3.5 nm) ferroelectric tunneling junctions for temporal data learning, IEEE Symposium on VLSI Technology, 2021, 通讯作者(34) Reliability Issues of Half-Selected Cells in Resistive Random Access Memory Array Integrated with 14nm FinFET, 2021 SILICON NANOELECTRONICS WORKSHOP (SNW), 2021, 通讯作者(35) Back-end-of-line-based resistive RAM in 0.13 μ m partially-depleted silicon-on-insulator process for highly reliable irradiation- resistant application, Ieee Electron Device Letters, 2020, 第 1 作者(36) First Demonstration of OxRRAM Integration on 14nm FinFet Platform and Scaling Potential Analysis towards Sub-10nm Node, 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020, 第 1 作者(37) Back-end-of-line-based resistive RAM in 0.13 μ m partially-depleted silicon-on-insulator process for highly reliable irradiation- resistant application, Ieee Electron Device Letters, 2020, 第 1 作者(38) First Demonstration of OxRRAM Integration on 14nm FinFet Platform and Scaling Potential Analysis towards Sub-10nm Node, 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020, 第 1 作者(39) Memory Switching and Threshold Switching in a 3D Nanoscaled NbOX System, IEEE ELECTRON DEVICE LETTERS, 2019, 第 6 作者(40) Uniformity and Endurance Enhancement of Valance Changed Resistive Switching Memory (VCM) by a New Pulse Method, 2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2019, 通讯作者(41) A 0.75V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique, IEICE ELECTRONICS EXPRESS, 2019, 第 5 作者(42) Composition-Dependent Ferroelectric Properties in Sputtered HfXZr1-XO2 Thin Films, IEEE ELECTRON DEVICE LETTERS, 2019, 第 9 作者(43) Suppression of Filament Overgrowth in Conductive Bridge Random Access Memory by Ta2O5/TaOx Bi-Layer Structure, NANOSCALE RESEARCH LETTERS, 2019, 通讯作者(44) Memory Switching and Threshold Switching in a 3D Nanoscaled NbOX System, IEEE ELECTRON DEVICE LETTERS, 2019, 第 6 作者(45) Uniformity and Endurance Enhancement of Valance Changed Resistive Switching Memory (VCM) by a New Pulse Method, 2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2019, 通讯作者(46) A 0.75V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique, IEICE ELECTRONICS EXPRESS, 2019, 第 5 作者(47) Composition-Dependent Ferroelectric Properties in Sputtered HfXZr1-XO2 Thin Films, IEEE ELECTRON DEVICE LETTERS, 2019, 第 9 作者(48) Suppression of Filament Overgrowth in Conductive Bridge Random Access Memory by Ta2O5/TaOx Bi-Layer Structure, NANOSCALE RESEARCH LETTERS, 2019, 通讯作者(49) Unveiling the Switching Mechanism of a TaOx/HfO2 Self-Selective Cell by Probing the Trap Profiles With RTN Measurements, IEEE ELECTRON DEVICE LETTERS, 2018, 第 4 作者(50) 1T1R结构RRAM的故障可测性设计, Fault Measurability Design of the RRAM Based on 1T1R Structure, 半导体技术, 2018, 第 2 作者(51) Self-Rectifying and Forming-Free Resistive-Switching Device for Embedded Memory Application, IEEE ELECTRON DEVICE LETTERS, 2018, 第 5 作者(52) 40×retention improvement by eliminating resistance relaxation with high temperature forming in 28 nm RRAM chip, IEEE International Electron Devices Meeting, 2018, 第 1 作者(53) 40x Retention Improvement by Eliminating Resistance Relaxation with High Temperature Forming in 28 nm RRAM Chip, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 1 作者(54) Analysis of tail bits generation of multilevel storage in resistive switching memory, Analysis of tail bits generation of multilevel storage in resistive switching memory, 中国物理B:英文版, 2018, 第 2 作者(55) Classification of Three-Level Random Telegraph Noise and Its Application in Accurate Extraction of Trap Profiles in Oxide-Based Resistive Switching Memory, IEEE ELECTRON DEVICE LETTERS, 2018, 第 3 作者(56) Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 8 作者(57) The Impact of RTN Signal on Array Level Resistance Fluctuation of Resistive Random Access Memory, IEEE ELECTRON DEVICE LETTERS, 2018, 第 4 作者(58) Analysis of tail bits generation of multilevel storage in resistive switching memory, CHINESE PHYSICS B, 2018, 通讯作者(59) Switching and Failure Mechanism of Self-selective Cell in 3D VRRAM by RTN-based Defect Tracking Technique, 2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2018, 第 4 作者(60) Unveiling the Switching Mechanism of a TaOx/HfO2 Self-Selective Cell by Probing the Trap Profiles With RTN Measurements, IEEE ELECTRON DEVICE LETTERS, 2018, 第 4 作者(61) 1T1R结构RRAM的故障可测性设计, Fault Measurability Design of the RRAM Based on 1T1R Structure, 半导体技术, 2018, 第 2 作者(62) Self-Rectifying and Forming-Free Resistive-Switching Device for Embedded Memory Application, IEEE ELECTRON DEVICE LETTERS, 2018, 第 5 作者(63) 40×retention improvement by eliminating resistance relaxation with high temperature forming in 28 nm RRAM chip, IEEE International Electron Devices Meeting, 2018, 第 1 作者(64) 40x Retention Improvement by Eliminating Resistance Relaxation with High Temperature Forming in 28 nm RRAM Chip, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 1 作者(65) Analysis of tail bits generation of multilevel storage in resistive switching memory, Analysis of tail bits generation of multilevel storage in resistive switching memory, 中国物理B:英文版, 2018, 第 2 作者(66) Classification of Three-Level Random Telegraph Noise and Its Application in Accurate Extraction of Trap Profiles in Oxide-Based Resistive Switching Memory, IEEE ELECTRON DEVICE LETTERS, 2018, 第 3 作者(67) Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 8 作者(68) The Impact of RTN Signal on Array Level Resistance Fluctuation of Resistive Random Access Memory, IEEE ELECTRON DEVICE LETTERS, 2018, 第 4 作者(69) Analysis of tail bits generation of multilevel storage in resistive switching memory, CHINESE PHYSICS B, 2018, 通讯作者(70) Switching and Failure Mechanism of Self-selective Cell in 3D VRRAM by RTN-based Defect Tracking Technique, 2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2018, 第 4 作者(71) Complementary Switching in 3D Resistive Memory Array, ADVANCED ELECTRONIC MATERIALS, 2017, 第 2 作者(72) Endurance characterization of the Cu-dope HfO2 based selection device with One Transistor-One Selector structure, 2017 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM), 2017, 第 2 作者(73) Uniformity and Retention Improvement of TaOx-Based Conductive Bridge Random Access Memory by CuSiN Interfacial Layer Engineering, IEEE ELECTRON DEVICE LETTERS, 2017, 第 3 作者(74) Highly uniform and nonlinear selection device based on trapezoidal band structure for high density nanocrossbar memory array, NANO RESEARCH, 2017, 第 2 作者(75) Variability Improvement of TiOx/Al2O3 Bilayer Nonvolatile Resistive Switching Devices by Interfacial Band Engineering with an Ultrathin Al2O3 Dielectric Material, ACS OMEGA, 2017, 第 2 作者(76) Complementary Switching in 3D Resistive Memory Array, ADVANCED ELECTRONIC MATERIALS, 2017, 第 2 作者(77) Endurance characterization of the Cu-dope HfO2 based selection device with One Transistor-One Selector structure, 2017 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM), 2017, 第 2 作者(78) Uniformity and Retention Improvement of TaOx-Based Conductive Bridge Random Access Memory by CuSiN Interfacial Layer Engineering, IEEE ELECTRON DEVICE LETTERS, 2017, 第 3 作者(79) Highly uniform and nonlinear selection device based on trapezoidal band structure for high density nanocrossbar memory array, NANO RESEARCH, 2017, 第 2 作者(80) Variability Improvement of TiOx/Al2O3 Bilayer Nonvolatile Resistive Switching Devices by Interfacial Band Engineering with an Ultrathin Al2O3 Dielectric Material, ACS OMEGA, 2017, 第 2 作者(81) Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells, Tech. Dig.-Int. Electron Devices Meet (IEDM), 2015, 第 2 作者(82) Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells, Tech. Dig.-Int. Electron Devices Meet (IEDM), 2015, 第 2 作者
科研活动
科研项目
( 1 ) 阻变存储器阵列可靠性的拖尾效应研究, 负责人, 国家任务, 2019-01--2021-12( 2 ) 具有多时间尺度神经动力学的忆阻器件研究, 负责人, 国家任务, 2021-12--2026-11( 3 ) XXXXX配套技术及验证, 负责人, 中国科学院计划, 2021-01--2023-12( 4 ) 基于阻变存储器的阵列控制器芯片研发及示范应用, 负责人, 地方任务, 2020-06--2022-06( 5 ) 中科院青年创新促进会优秀会员, 负责人, 中国科学院计划, 2023-01--2025-12
参与会议
(1)Scaling Potential Analysis for the CMOS Compatible Ox-RRAM 2021-05-09(2)Integration of Resistive switching memory on Advanced Technology node 2021-04-09(3)First Demonstration of OxRRAM Integration on 14nm FinFet Platform and Scaling Potential Analysis towards Sub-10nm Node 2020-12-06(4)阻变存储器及微缩研究 全国电子信息青年科学家论坛暨第三届半导体青年学术会议 2020-10-29(5)40×retention improvement by eliminating resistance relaxation with high temperature forming in 28 nm RRAM chip 2018-12-15