基本信息

刘岳阳  研究员  博导  国家高层次青年人才

中国科学院半导体研究所  

电子邮件: yueyangliu@semi.ac.cn
通信地址: 北京市海淀区清华东路甲35号中科院半导体所2号楼501
邮政编码:

研究领域

半导体器件原子级精度模拟

​晶体管可靠性物理与设计

半导体材料、界面与缺陷计算


招生信息

   
招生专业
070205-凝聚态物理
招生方向
半导体器件可靠性物理,半导体器件界面研究,半导体材料缺陷计算
招生专业2

电子信息

教育背景

2012-09--2017-06   湖南大学   获得博士学位
2008-09--2012-06   湖南大学   获得学士学位

工作经历

   
工作简历
2023-03~现在, 中国科学院半导体研究所, 研究员
2020-11~2023-03,中国科学院半导体研究所, 副研究员
2019-02~2020-04,美国劳伦斯伯克利国家实验室, 访问学者
2017-07~2020-10,中国科学院半导体研究所, 博士后

出版信息

   
发表论文
(1) Reliability challenges of gate dielectric materials in transistors, Inf. Funct. Mater., 2025, 第 2 作者  通讯作者
(2) Atomic Level Insight into the Variation and Tunability of Band Alignment between Si and Amorphous SiO2/HfO2, CHINESE PHYSICS LETTERS, 2025, 第 5 作者  通讯作者
(3) Strain- and dipole-induced interface states in gate-all-around transistors: Properties and implications for application, Phys. Rev. Applied, 2025, 第 1 作者  通讯作者
(4) Towards Understanding Cryogenic Reliability in FinFETs under Hot Carrier Stress: New Findings on Ge Migration, and Impacts of Tail States Evolution, VLSI, 2025, 第 2 作者  通讯作者
(5) Carrier injection induced degradation of nitrogen passivated SiC-SiO2 interface simulated by time-dependent density functional theory, Journal of Applied Physics, 2024, 第 2 作者  通讯作者
(6) MARS: a Multiscale Ab initio Reliability Simulator for Advanced Si and 2D Material Based MOSFETs, IEDM, 2024, 第 1 作者  通讯作者
(7) Reliability Improvement of 2-D WSe2 FETs by Regulating Charge Trapping: An Ab Initio Demonstration, IEEE TED, 2024, 第 2 作者  通讯作者
(8) Towards Understanding the Dynamic Variation in FinFET at Cryogenic Temperature: New Observations and Physical Modeling, IEDM, 2024, 第 3 作者  通讯作者
(9) Wide-Spectrum Polarization-Sensitive Photodetector Based on Spontaneous GaTe/Ga-2(TexO1-x)(5 )Heterostructure, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 第 7 作者
(10) New Insights into the Interface Trap Generation during Hot Carrier Degradation: Impacts of Full-band Electronic Resonance, (100) vs (110), and nMOS vs pMOS, International Electron Devices Meeting (IEDM), 2023, 第 2 作者  通讯作者
(11) Polarimetric Image Sensor and Fermi Level Shifting Induced Multichannel Transition Based on 2D PdPS, ADVANCED MATERIALS, 2022, 第 9 作者  通讯作者
(12) The mechanism of improving germanium metal-oxide-semiconductor field-effect transistors' reliability by high-k dielectric and yttrium-doping: From the view of charge trapping, Journal of Applied Physics, 2022, 第 5 作者  通讯作者
(13) The role of surface pretreatment by low temperature O-2 gas annealing for beta-Ga2O3 Schottky barrier diodes, APPLIED PHYSICS LETTERS, 2022, 第 6 作者  通讯作者
(14) A Gate Programmable van der Waals Metal-Ferroelectric-Semiconductor Vertical Heterojunction Memory, ADVANCED MATERIALS, 2022, 第 16 作者  通讯作者
(15) Giant tunnel magnetoresistance in two-dimensional van der Waals magnetic tunnel junctions: Ag/CrI3/MoSi2N4/CrI3/Ag, PHYSICAL REVIEW B, 2022, 第 5 作者  通讯作者
(16) Spin-Filter Magnetic Tunnel Junctions Based on A-Type Antiferromagnetic CrSBr with Giant Tunnel Magnetoresistance, MAGNETOCHEMISTRY, 2022, 第 2 作者  通讯作者
(17) Vertical strain and electric field tunable band alignment in type-II ZnO/MoSSe van der Waals heterostructures, PHYSICAL CHEMISTRY CHEMICAL PHYSICS, 2021, 第 5 作者  通讯作者
(18) Electronically induced defect creation at semiconductor/oxide interface revealed by time-dependent density functional theory, PHYSICAL REVIEW B, 2021, 第 1 作者
(19) Defects Induced Charge Trapping/Detrapping and Hysteresis Phenomenon in MoS2 Field-Effect Transistors: Mechanism Revealed by Anharmonic Marcus Charge Transfer Theory, ACS APPLIED MATERIALS & INTERFACES, 2021, 第 2 作者
(20) Cross-Substitution Promoted Ultrawide Bandgap up to 4.5 eV in a 2D Semiconductor: Gallium Thiophosphate, ADVANCED MATERIALS, 2021, 第 5 作者
(21) Three-Dimensional Mechanistic Modeling of Gate Leakage Current in High-kappa MOSFETs, PHYSICAL REVIEW APPLIED, 2020, 第 2 作者
(22) First principles study of Schottky barriers at Ga2O3(100)/metal interfaces, RSC ADVANCES, 2020, 第 4 作者  通讯作者
(23) 半导体器件可靠性的物理机制研究, 2020, 第 1 作者
(24) Distinguishing interfacial hole traps in (110), (100) high-k gate stack, 2019 IEEE International Reliability Physics Symposium : Volume 2 of 2, 2019, 第 1 作者
(25) Characterizing the Charge Trapping across Crystalline and Amorphous Si/SiO2/HfO2 Stacks from First-Principle Calculations, PHYSICAL REVIEW APPLIED, 2019, 第 1 作者
(26) Ab Initio Investigation of Charge Trapping Across the Crystalline-Si-Amorphous-SiO2 Interface, PHYSICAL REVIEW APPLIED, 2019, 第 1 作者
(27) An efficient mechanism for enhancing the thermoelectricity of nanoribbons by blocking phonon transport in 2d materials, JOURNAL OF PHYSICS-CONDENSED MATTER, 2018, 第 1 作者
(28) Physics of hole trapping process in high-k gate stacks: A direct simulation formalism for the whole interface system combining density-functional theory and Marcus theory, 2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2018, 第 1 作者
(29) Anomalous thermal anisotropy of two-dimensional nanoplates of vertically grown MoS2, APPLIED PHYSICS LETTERS, 2017, 第 2 作者
(30) Effect of room temperature lattice vibration on the electron transport in graphene nanoribbons, APPLIED PHYSICS LETTERS, 2017, 第 1 作者
(31) Triggering piezoelectricity directly by heat to produce alternating electric voltage, APPLIED PHYSICS LETTERS, 2016, 第 1 作者
(32) Conjunction of standing wave and resonance in asymmetric nanowires: a mechanism for thermal rectification and remote energy accumulation, SCIENTIFIC REPORTS, 2015, 第 1 作者
(33) An important mechanism for thermal rectification in graded nanowires, APPLIED PHYSICS LETTERS, 2014, 第 1 作者
(34) Core-shell nanowire serves as heat cable, APPLIED PHYSICS LETTERS, 2013, 第 1 作者

科研活动

科研项目
( 1 ) HKMG复杂氧化物异质结界面多尺度工艺及可靠性建模仿真技术, 负责人, 境内委托项目, 2025-01--2025-12
( 2 ) 高MOS沟道迁移率及其低温电子输运与器件研究, 负责人, 国家任务, 2024-12--2029-11
( 3 ) 工业模拟芯片可靠性模型及仿真方法研究, 参与, 国家任务, 2022-10--2025-09
( 4 ) FinFET和GAAFET热载流子可靠性的原子级动力学理论研究, 负责人, 国家任务, 2022-01--2025-12
( 5 ) 半导体氧化层多界面缺陷中心电荷俘获机理研究, 负责人, 国家任务, 2021-01--2023-12
参与会议
(1)Multiscale Ab initio Reliability Simulator (MARS) for advanced MOSFETs   第16届IEEE国际专用集成电路会议(ASICON)   刘岳阳   2025-10-21
(2)晶体管可靠性原子级精度模拟   第二十五届全国半导体物理学术会议   刘岳阳   2025-10-16
(3)The localized interface/channel states in Gate-All-Around transistors (GAAFETs): physical origins and distribution   第55届半导体界面专家会议SISC   刘岳阳   2024-12-12
(4)MARS: a Multiscale Ab initio Reliability Simulator for Advanced Si and 2D Material Based MOSFETs   第70届国际电子器件会议IEDM   刘岳阳,徐光华   2024-12-10
(5)Atomic level to device level simulation of transistor’s reliability   国际EDA会议   Yue-Yang Liu   2024-05-10
(6)半导体器件可靠性相关缺陷物理   第二届全国半导体缺陷研讨会   刘岳阳   2024-04-12