基本信息
黄明强  男  硕导  中国科学院深圳先进技术研究院
电子邮件: mq.huang2@siat.ac.cn
通信地址: 广东省深圳市南山区中科院深圳先进院
邮政编码:

研究领域

集成电路IC设计、微电子技术

招生信息

   
招生专业
085400-电子信息
080903-微电子学与固体电子学
招生方向
集成电路设计
微电子器件
高能效计算

教育背景

2013-09--2018-06   华中科技大学   博士学位
2009-09--2013-06   华中科技大学   学士

工作经历

2024.01 -- 至今        中国科学院深圳先进技术研究院 研究员

2019.11 -- 2023.12   中国科学院深圳先进技术研究院 副研究员

2018.09 -- 2019.11   新加坡南洋理工大学 博士后

出版信息


发表论文
(1) Mingqiang Huang; Ao Shen; Kai Li; Haoxiang Peng; Boyu Li; Yupeng Su; Hao Yu ; EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models, IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, Mingqiang Huang; Ao Shen; Kai Li; Haoxiang Peng; Boyu Li; Yupeng Su; Hao Yu ; EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models, IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, 第 1 作者
(2) Wen, Wanting; Zhao, Guangchao; Hu, Wanbo; Li, Ziye; Wang, Xingli; Friedman, Eby G.; Tay, Beng Kang; Ke, Shaolin; Huang, Mingqiang ; High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, Wen, Wanting; Zhao, Guangchao; Hu, Wanbo; Li, Ziye; Wang, Xingli; Friedman, Eby G.; Tay, Beng Kang; Ke, Shaolin; Huang, Mingqiang ; High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 
(3) Guangchao Zhao; Zhiwei Zeng; Xingli Wang; Abdelrahman G. Qoutb; Philippe Coquet; Eby G. Friedman; Beng Kang Tay; Mingqiang Huang ; Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms, IEEE Transactions on Emerging Topics in Computing, 2023, 1(1), Guangchao Zhao; Zhiwei Zeng; Xingli Wang; Abdelrahman G. Qoutb; Philippe Coquet; Eby G. Friedman; Beng Kang Tay; Mingqiang Huang ; Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms, IEEE Transactions on Emerging Topics in Computing, 2023, 1(1), IEEE Transactions on Emerging Topics in Computing, 2023, 
(4) Mingqiang Huang; Junyi Luo; Chenchen Ding; Zikun Wei; Sixiao Huang; Hao Yu ; An Integer Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge, IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12): 5289-5301, Mingqiang Huang; Junyi Luo; Chenchen Ding; Zikun Wei; Sixiao Huang; Hao Yu ; An Integer Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge, IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12): 5289-5301, IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 第 1 作者
(5) Mingqiang Huang; Yucen Liu; Changhai Man; Kai Li; Quan Cheng; Wei Mao; Hao Yu ; A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1, 2022, 69(9): 3619-3631, Mingqiang Huang; Yucen Liu; Changhai Man; Kai Li; Quan Cheng; Wei Mao; Hao Yu ; A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS���I: REGULAR PAPERS 1, 2022, 69(9): 3619-3631, IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 第 1 作者
(6) AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence, 2021, 第 2 作者
(7) Winograd Algorithm for AdderNet, 2021, 第 3 作者
(8) Global-Gate Controlled One-Transistor One-Digital-Memristor Structure for Low-Bit Neural Network, IEEE ELECTRON DEVICE LETTERS, 2021, 第 1 作者  通讯作者
(9) Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks, ADVANCED INTELLIGENT SYSTEMS, 2021, 第 10 作者  通讯作者
(10) Flexible electronic synapse enabled by ferroelectric field effect transistor for robust neuromorphic computing, APPLIED PHYSICS LETTERS, 2020, 第 11 作者  通讯作者
(11) A transverse tunnelling field-effect transistor made from a van der Waals heterostructure, NATURE ELECTRONICS, 2020, 第 2 作者
(12) Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials, APPLIED SCIENCES, 2019, 第 1 作者
(13) High-performance two-dimensional transistors and circuits, 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, 第 3 作者
(14) Optimized Transport Properties in Lithium Doped Black Phosphorus Transistors, IEEE ELECTRON DEVICE LETTERS, 2018, 第 4 作者
(15) High Performance Black Phosphorus Electronic and Photonic Devices with HfLaO Dielectric, IEEE ELECTRON DEVICE LETTERS, 2018, 第 3 作者
(16) Multifunctional high-performance van der Waals heterostructures, NATURE NANOTECHNOLOGY, 2017, 第 1 作者
(17) Broadband Black-Phosphorus Photodetectors with High Responsivity, ADVANCED MATERIALS, 2016, 第 1 作者
(18) Performance Potential and Limit of MoS2 Transistors, ADVANCED MATERIALS, 2015, 第 5 作者

科研活动

   
科研项目
( 1 ) 存算融合架构中的全模式混合精度计算, 负责人, 国家任务, 2025-01--2027-12
( 2 ) 3D存算一体芯片及其通用型网络映射方案研究, 负责人, 国家任务, 2022-08--2027-07
( 3 ) 1bit神经网络FPGA功耗验证, 负责人, 境内委托项目, 2022-04--2022-09
( 4 ) 忆阻器高能效在线学习方案关键问题研究, 负责人, 国家任务, 2022-01--2024-12
( 5 ) 突触电子器件及其在感知神经网络中的应用, 负责人, 地方任务, 2020-11--2023-11
( 6 ) FPGA 卷积神经网络, 负责人, 境内委托项目, 2020-07--2021-06