基本信息
杨红  女  硕导  中国科学院微电子研究所
电子邮件: yanghong@ime.ac.cn
通信地址: 北京市朝阳区北土城西路3号
邮政编码:

招生信息

   
招生专业
080903-微电子学与固体电子学
085400-电子信息
招生方向
新型器件可靠性与失效分析
新型器件可靠性与失效分析

教育背景

2015-09--2019-06   中国科学院大学   工学博士
2002-09--2005-07   北京大学   理科硕士
1998-09--2002-07   北京大学   理科学士

工作经历

   
工作简历
2020-08~现在, 中国科学院微电子研究所, 研究员
2015-09~2019-06,中国科学院大学, 工学博士
2011-08~2020-07,中国科学院微电子研究所, 副研究员
2005-09~2011-08,韩国三星电子半导体事业部(韩国), 工程师/高级工程师
2002-09~2005-07,北京大学, 理科硕士
1998-09~2002-07,北京大学, 理科学士

专利与奖励

   
专利成果
( 1 ) 半导体器件制造方法, 2022, 第 1 作者, 专利号: CN114121804A

( 2 ) 半导体结构及其形成方法, 2021, 第 5 作者, 专利号: CN113809011A

( 3 ) 一种半导体结构及其制作方法, 2021, 第 4 作者, 专利号: CN113540342A

( 4 ) 一种堆叠纳米线或片CMOS器件制备方法, 2021, 第 5 作者, 专利号: CN110729248B

( 5 ) 半导体结构与其制作方法, 2021, 第 3 作者, 专利号: CN113314500A

( 6 ) 一种半导体结构及其制作方法, 2021, 第 4 作者, 专利号: CN113140448A

( 7 ) 一种半导体结构及其形成方法, 2021, 第 5 作者, 专利号: CN112768342A

( 8 ) 确定器件故障点的测试方法及装置、存储介质, 2021, 第 8 作者, 专利号: CN112649699A

( 9 ) 半导体结构及其形成方法, 2021, 第 5 作者, 专利号: CN112466945A

( 10 ) 一种电子器件及其制作方法、集成电路和电子设备, 2020, 第 6 作者, 专利号: CN111211110A

( 11 ) 半导体器件及其制备方法、集成电路及电子设备, 2020, 第 5 作者, 专利号: CN111180520A

( 12 ) 一种半导体器件及其制备方法、集成电路及电子设备, 2020, 第 5 作者, 专利号: CN111180519A

( 13 ) 一种堆叠纳米线或片环栅CMOS器件的制备方法, 2020, 第 5 作者, 专利号: CN110896055A

( 14 ) 一种鳍状结构的制备方法以及半导体器件的制备方法, 2020, 第 2 作者, 专利号: CN110752156A

( 15 ) 一种与堆叠纳米线或片兼容的输入输出器件及制备方法, 2020, 第 2 作者, 专利号: CN110739272A

( 16 ) 一种接触孔制备方法, 2019, 第 3 作者, 专利号: CN110634801A

( 17 ) 一种自对准双重图形的制备方法、硬掩模图案, 2019, 第 3 作者, 专利号: CN110335813A

( 18 ) 半导体器件及其制造方法, 2019, 第 1 作者, 专利号: CN109950258A

( 19 ) 纳米线器件的制作方法, 2019, 第 5 作者, 专利号: CN109830525A

( 20 ) 半导体结构与其制作方法, 2019, 第 3 作者, 专利号: CN109712871A

( 21 ) 半导体器件及其制造方法, 2019, 第 4 作者, 专利号: CN109427876A

( 22 ) CMOS器件及其制造方法, 2019, 第 2 作者, 专利号: CN105470256B

( 23 ) 半导体结构与其制作方法, 2018, 第 4 作者, 专利号: CN108878263A

( 24 ) P type MOSFET, 2018, 第 4 作者, 专利号: US10056261(B2)

( 25 ) 一种基于可变功函数栅极的晶体管器件及其制备方法, 2017, 第 3 作者, 专利号: CN107039283A

( 26 ) 一种基于单原子层沉积的金属生长方法, 2017, 第 3 作者, 专利号: CN106987825A

( 27 ) 半导体晶体管金属栅的集成工艺方法, 2017, 第 1 作者, 专利号: CN106601674A

( 28 ) 一种提取半导体缺陷能级的方法及系统, 2017, 第 3 作者, 专利号: CN106556789A

( 29 ) 半导体器件及其制造方法, 2017, 第 4 作者, 专利号: CN106471612A

( 30 ) CMOS器件及其制造方法, 2016, 第 2 作者, 专利号: CN105470256A

( 31 ) 一种后栅工艺中的栅极形成方法, 2015, 第 3 作者, 专利号: CN104779150A

( 32 ) 半导体器件制造方法, 2015, 第 4 作者, 专利号: CN104766823A

( 33 ) 半导体设置及其制造方法, 2015, 第 7 作者, 专利号: CN104716171A

( 34 ) 降低栅介质的泄漏电流的方法, 2015, 第 1 作者, 专利号: CN104377126A

( 35 ) 半导体器件制造方法, 2015, 第 3 作者, 专利号: CN104377168A

( 36 ) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, 2015, 第 4 作者, 专利号: US2015048458(A1)

( 37 ) P TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME, 2015, 第 4 作者, 专利号: US20150041925A1

( 38 ) P TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME, 2015, 第 4 作者, 专利号: US20150041925(A1)

( 39 ) 金属栅电极等效功函数调节方法, 2015, 第 1 作者, 专利号: CN104347411A

( 40 ) N型MOSFET及其制造方法, 2014, 第 4 作者, 专利号: CN103855008A

( 41 ) P型MOSFET及其制造方法, 2014, 第 4 作者, 专利号: CN103855014A

( 42 ) 具有双功函数金属栅的互补场效应晶体管及其制造方法, 2014, 第 4 作者, 专利号: CN103579113A

( 43 ) 栅极结构的形成方法、半导体器件的形成方法以及半导体器件, 2014, 第 1 作者, 专利号: CN103545191A

( 44 ) 栅极结构的形成方法、半导体器件的形成方法以及半导体器件, 2014, 第 1 作者, 专利号: CN103545190A

( 45 ) 栅极结构、半导体器件和两者的形成方法, 2014, 第 1 作者, 专利号: CN103545189A

( 46 ) 一种低功函数金属栅形成方法, 2014, 第 4 作者, 专利号: CN103545182A

( 47 ) CMOS器件及其制造方法, 2011, 第 2 作者, 专利号: CN101958328A

( 48 ) 半导体器件制造方法, 2006, 第 3 作者, 专利号: CN1787186A

出版信息

   
发表论文
(1) Recovery Behavior of Interface Traps After Negative Bias Temperature Instability Stress in p-FinFETs Featuring Fast Trap Characterization Technique, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 通讯作者
(2) Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 通讯作者
(3) Study of the yield improvement and reliability of 28 nm advanced chips based on structural analysis, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2021, 通讯作者
(4) An Investigation of Field Reduction Effect on NBTI Parameter Characterization and Lifetime Prediction Using a Constant Field Stress Method, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2020, 通讯作者
(5) Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2020, 第 3 作者
(6) Study of selective isotropic etching Si1-xGex in process of nanowire transistors, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2020, 第11作者
(7) 部分耗尽SOI MOSFET NBTI效应研究, Study on NBTI Effect of PDSOI MOSFET, 航空科学技术, 2020, 第 5 作者
(8) Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs, 2020 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2020, 
(9) Impact of Charges at Ferroelectric/Interlayer Interface on Depolarization Field of Ferroelectric FET With Metal/Ferroelectric/Interlayer/Si Gate-Stack, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 第 7 作者
(10) Comparative study on NBTI kinetics in Si p-FinFETs with B2H6-based and SiH4-based atomic layer deposition tungsten (ALD W) filling metal, MICROELECTRONICS RELIABILITY, 2020, 通讯作者
(11) Investigation on thermal stability of Si0.7Ge0.3/Si stacked multilayer for gate-all-around MOSFETS, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 第 14 作者
(12) Degradation Mechanism of Short Channel p-FinFETs under Hot Carrier Stress and Constant Voltage Stress, 2020 IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2020, 
(13) Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2020, 第 13 作者
(14) Influence of an ALD TiN capping layer on the PBTI characteristics of n-FinFET with ALD HfO2/TiN-capping/TiAl gate stacks, Influence of an ALD TiN capping layer on the PBTI characteristics of n-FinFET with ALD HfO2/TiN-capping/TiAl gate stacks, SCIENCE CHINA-INFORMATION SCIENCES, 2020, 第 1 作者
(15) Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs, IEEE ELECTRON DEVICE LETTERS, 2020, 通讯作者
(16) Experimental study of the ultrathin oxides on SiGe alloy formed by low-temperature ozone oxidation, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2020, 第 8 作者
(17) Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors, NANOMATERIALS, 2020, 第 15 作者
(18) Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 第 6 作者
(19) Fabrication technique of the Si0.5Ge0.5 Fin for the high mobility channel FinFET device, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 第 13 作者
(20) Impact of Electron trapping on Energy Distribution Characterization of NBTI-Related Defects for Si p-FinFETs, 2020 IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2020, 
(21) A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm, MATERIALS, 2020, 第 16 作者
(22) State of the Art and Future Perspectives in Advanced CMOS Technology, NANOMATERIALS, 2020, 第 13 作者
(23) A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown, JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2019, 第11作者
(24) Identification of a suitable passivation route for high-k/SiGe interface based on ozone oxidation, APPLIED SURFACE SCIENCE, 2019, 第 4 作者
(25) 高k/金属栅结构CMOS器件的界面调控及可靠性机理研究, Study on Mechanisms of Interface Modulation and Reliability in CMOS with High-k/Metal Gate, 2019, 第 1 作者
(26) Experimental Investigation of Remote Coulomb Scattering on Mobility Degradation of Ge pMOSFET by Various PDA Ambiences, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 第 7 作者
(27) High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2019, 第11作者
(28) Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation, ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2019, 第 6 作者
(29) Evaluation of hole mobility degradation by remote Coulomb scattering in Ge pMOSFETs, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2019, 第 8 作者
(30) Miniaturization of CMOS, MICROMACHINES, 2019, 第11作者
(31) Comprehensive investigation of the interfacial charges and dipole in GeOx/AL(2)O(3) gate stacks of Ge MOS capacitor by postdeposition annealing, JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 第 7 作者
(32) Identification of interfacial defects in a Ge gate stack based on ozone passivation, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2018, 第 7 作者
(33) Effects of high-energy proton irradiation on separate absorption and multiplication GaN avalanche photodiode, Effects of high-energy proton irradiation on separate absorption and multiplication GaN avalanche photodiode, 核技术:英文版, 2018, 
(34) Physical Mechanism Underlying the Time Exponent Shift in the Ultra-fast NBTI of High-k/Metal gated p-CMOSFETs, 2018 25TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2018, 
(35) Impact of ALD TiN Capping Layer on Interface Trap and Channel Hot Carrier Reliability of HKMG nMOSFETs, IEEE ELECTRON DEVICE LETTERS, 2018, 第 1 作者
(36) Understanding dipole formation at dielectric/dielectric hetero-interface, APPLIED PHYSICS LETTERS, 2018, 第 7 作者
(37) Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process, IEEE ELECTRON DEVICE LETTERS, 2018, 第 10 作者
(38) 高k HfO2栅介质淀积后退火工艺研究, Study on Post Deposition Annealing Process of the High-k HfO2 Gate Dielectric, 半导体技术, 2018, 第 3 作者
(39) Crystallization behaviors of ultrathin Al-doped HfO2 amorphous films grown by atomic layer deposition, Chin. Phys. B, 2017, 第 9 作者
(40) Hole mobility degradation by remote Coulomb scattering and charge distribution in Al2O3/GeOx gate stacks in bulk Ge pMOSFET with GeOx grown by ozone oxidation, JOURNAL OF PHYSICS D-APPLIED PHYSICS, 2017, 第 5 作者
(41) Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process, CHINESE PHYSICS B, 2017, 第 2 作者
(42) Crystallization behaviors of ultrathin Al-doped HfO_2 amorphous films grown by atomic layer deposition, CHINESE PHYSICS B, 2017, 第 2 作者
(43) Series resistance effect on time zero dielectrics breakdown characteristics of MOSCAP with ultra-thin EOT high-k/metal gate stacks, JOURNAL OF SEMICONDUCTORS, 2016, 第 2 作者
(44) FOI FinFET with Ultra-low Parasitic Resistance Enabled by Fully Metallic Source and Drain Formation on Isolated Bulk-Fin, 2016 IEEE International Electron Devices Meeting: IEDM 2016, San Francisco, California, USA, 3-7 December 2016, pages 452-929, v.2, 2016, 第 4 作者
(45) Accurate lifetime prediction for channel hot carrier stress on sub-1 nm equivalent oxide thickness HK/MG nMOSFET with thin titanium nitride capping layer, MICROELECTRONICS RELIABILITY, 2016, 通讯作者
(46) Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-K metal gate NMOSFET with kMC TDDB simulations, Chinese Physics B, 2016, 第 2 作者
(47) Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-kappa metal gate NMOSFET with kMC TDDB simulations, CHINESE PHYSICS B, 2016, 第 2 作者
(48) Temperature-and voltage-dependent trap generation model in high-kappa metal gate MOS device with percolation simulation, CHINESE PHYSICS B, 2016, 第 2 作者
(49) Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation, Chinese Physics B, 2016, 第 2 作者
(50) Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process, CHINESE PHYSICS B, 2015, 第 2 作者
(51) Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 第 7 作者
(52) Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs, Journal of Semiconductors, 2015, 第 9 作者
(53) Energy distribution extraction of negative charges responsible for positive bias temperature instability, CHINESE PHYSICS B, 2015, 第 2 作者
(54) Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process, CHINESE PHYSICS B, 2015, 第 2 作者
(55) Electric dipole formation at high-k dielectric/SiO_2 interface, JOURNAL OF SEMICONDUCTORS, 2015, 第 3 作者
(56) Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process, Journal of Semiconductors, 2015, 第 5 作者
(57) TDDB characteristic and breakdown mechanism of ultra-thin SiO_2/HfO_2 bilayer gate dielectrics, JOURNAL OF SEMICONDUCTORS, 2014, 第 2 作者
(58) Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process, Journal of Semiconductors, 2014, 第 2 作者
(59) The effects of process condition of Top-TiN and TaN thickness on the effective work function of MOSCAP with high-k/metal gate stacks, JOURNAL OF SEMICONDUCTORS, 2014, 第 2 作者
(60) Mitigation of reverse short channel effect with multilayer TiN Ti TiN metal gates in gate last Pmosfets, IEEE ELECTRON DEVICE LETTERS, 2014, 其他(合作组作者)
(61) Analysis of flatband voltage shift of metal/high-k/SiO_2/Si stack based on energy band alignment of entire gate stack, CHINESE PHYSICS B, 2014, 第 4 作者
(62) An effective work-function tuning method of nMOSCAP with high-k/metal gate by TiN/TaN double-layer stack thickness, JOURNAL OF SEMICONDUCTORS, 2014, 第 2 作者
(63) Impact of TaN as wet etch stop layer on device characteristics for dual metal HKMG last integration CMOSFETs, IEEE ELECTRON DEVICE LETTERS, 2013, 第 3 作者
(64) Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO_2 dielectric, CHINESE PHYSICS B, 2013, 第 3 作者
(65) Effect of low temperature annealing on the electrical properties of an MOS capacitor with a HfO_2 dielectric and a TiN metal gate, JOURNAL OF SEMICONDUCTORS, 2013, 第 4 作者
(66) A possible origin of core-level shift in SiO2/Si stacks, APPLIED PHYSICS LETTERS, 2013, 第 6 作者
(67) Physical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-fieldeffect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses, APPLIED PHYSICS LETTERS, 2013, 第 2 作者
(68) Reexamination of band offset transitivity employing oxide heterojunctions, APPLIED PHYSICS LETTERS, 2013, 第 6 作者
(69) Band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack, APPLIED PHYSICS LETTERS, 2012, 第 4 作者
(70) Band alignment of HfO2 on SiO2/Si structure, APPLIED PHYSICS LETTERS, 2012, 第 5 作者

科研活动

   
科研项目
( 1 ) 双金属栅CMOS器件的可靠性退化机制及其抑制方法研究, 负责人, 国家任务, 2014-01--2016-12
( 2 ) 基于半导体器件电学测试平台的可靠性自动化测试功能扩展与优化, 负责人, 中国科学院计划, 2017-09--2019-08
( 3 ) 器件可靠性技术研究, 负责人, 企业委托, 2016-01--2019-12
( 4 ) 高端芯片可靠性与可信任性评价分析关键技术, 参与, 地方任务, 2019-01--2021-12
( 5 ) 5纳米先导技术研究-5nm锗/锗硅高迁移率沟道三维器件及关键共性技术, 参与, 国家任务, 2017-01--2020-12
( 6 ) 3-1纳米集成电路新器件与先导工艺, 参与, 中国科学院计划, 2019-09--2020-10
( 7 ) 微纳器件与电路物理分析平台, 参与, 中国科学院计划, 2020-01--2020-12
( 8 ) 碳纳米管器件鲁棒性研究, 负责人, 国家任务, 2020-08--2023-08
( 9 ) 突破异质集成的新材料和器件原理研究, 参与, 国家任务, 2021-01--2024-12
参与会议
(1)A Fast DCIV Technique for Characterizing the Generation and Repassivation of Interface Traps Under DC/AC NBTI Stress/Recovery Condition in Si p-FinFETs   2021-04-30
(2)Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs   2020-04-30
(3)Comparison of NBTI kinetics in Replacement Metal Gate Si p-FinFETs featuring Atomic Layer Deposition Tungsten Filling Metal Using B2H6 and SiH4 Precursors   2019-07-01