设计工艺协同优化，基于机器学习的EDA设计，计算光刻

招收博士和硕士，希望学生有算法和编程基础，熟悉微电子设计/制造流程。

080903-微电子学与固体电子学

2000-09--2005-07 清华大学 获得博士学位
1995-09--1998-04 电子科技大学微电子所 获得硕士学位
1991-09--1995-07 电子科技大学 获得学士学位

博士

   

2005-07--2013-03 中国科学院微电子研究所 任职
1998-04--2000-04 电子科技大学微电子所 担任教师

半导体器件模型及其仿真

   

[1] 屈通, 韦亚一, 粟雅娟. 基于工艺窗口的冗余局部环路插入方法. CN: CN113097207A, 2021-07-09.
[2] 杨双, 韦亚一, 粟雅娟. 一种集成电路中金属线温度测量方法. CN: CN110617894B, 2020-12-22.
[3] 盖天洋, 韦亚一, 粟雅娟, 陈颖. 一种生成设计版图坏点检测模型的方法及检测坏点的方法. CN: CN111582309A, 2020-08-25.
[4] 盖天洋, 韦亚一, 粟雅娟, 陈颖. 一种版图特征提取的超参数确定方法、装置及介质. CN: CN111539177A, 2020-08-14.
[5] 王金枝, 韦亚一, 粟雅娟. 一种晶圆测试方法及装置. CN: CN111446179A, 2020-07-24.
[6] 何建芳, 韦亚一, 粟雅娟, 董立松, 张利斌, 苏晓菁, 陈睿, 马玲. 一种确定光刻工艺节点禁止周期的方法及仿真方法. CN: CN111025856A, 2020-04-17.
[7] 郭成, 韦亚一, 粟雅娟. 通孔层版图生成方法以及装置. CN: CN111027272A, 2020-04-17.
[8] 陈睿, 韦亚一, 唐明浩, 张利斌, 马乐, 粟雅娟, 董立松, 何建芳, 王文武. 一种基板及其制备方法. CN: CN110752180A, 2020-02-04.
[9] 杨双, 韦亚一, 粟雅娟. 一种金属栅温度测量方法. CN: CN110610871A, 2019-12-24.
[10] 于丽贤, 韦亚一, 粟雅娟. 一种双重版图的设计方法及系统. CN: CN106339519B, 2019-10-11.
[11] 粟雅娟, 贾昆鹏, 赵超, 战俊, 曹合适. 二维材料结构的制造方法和二维材料器件. CN: CN105895530B, 2019-03-19.
[12] 韦亚一, 赵利俊, 粟雅娟. 一种标准单元库的优化方法及系统. CN: CN105868449B, 2019-03-15.
[13] 盖天洋, 韦亚一, 粟雅娟, 陈颖. 一种版图测试图形提取方法、装置、设备及介质. CN: CN109360185A, 2019-02-19.
[14] 张利斌, 粟雅娟, 韦亚一. 一种扫描电子显微图像的三维重构方法. 中国: CN105590338B, 2018-08-10.
[15] 贾昆鹏, 粟雅娟, 朱慧珑, 赵超. 石墨烯结构、石墨烯器件及其制造方法. 中国: CN104779287B, 2018-02-02.
[16] 贾昆鹏, 粟雅娟, 朱慧珑, 赵超. 降低二维晶体材料接触电阻的方法. 中国: CN104253015B, 2017.12.22.
[17] 粟雅娟, 曹合适, 贾昆鹏, 战俊. 一种微纳机电开关及其制造方法. 中国: CN106298372A, 2017-01-04.
[18] 聂鹏飞, 朱慧珑, 粟雅娟, 贾昆鹏, 杨杰. 微纳尺度静电力开关及其制造方法. 中国: CN103964364A, 2014-08-06.
[19] 聂鹏飞, 粟雅娟, 朱慧珑, 赵超, 贾昆鹏, 杨杰. 互连结构及其制造方法. 中国: CN103943599A, 2014-07-23.
[20] 贾昆鹏, 粟雅娟, 聂鹏飞. 石墨烯测序器件及其制造方法. 中国: CN103789204A, 2014-05-14.
[21] 粟雅娟, 陈岚. 一种内建自测试装置及一种使用片上系统进行测试的系统. 中国: CN202837493U, 2013-03-27.
[22] 粟雅娟, 陈岚. 一种内建自测试装置. 中国: CN102495361A, 2012-06-13.
[23] 李平, 粟雅娟. 锗硅异质结低正向压降高速二极管. 中国: CN1161575, 1997-10-08.

   

[1] 蒲明博, 李向平, 张杨, 郑美玲, 粟雅娟, 曹耀宇, 曹暾, 徐挺, 段宣明, 冯帅, 孙玲. 芯片制造中的光学微纳加工技术前沿与挑战. 中国科学基金[J]. 2022, 36(3): 460-467, http://lib.cqvip.com/Qikan/Article/Detail?id=7107739582.
[2] Gai, Tianyang, Qu, Tong, Wang, Shuhan, Su, Xiaojing, Xu, Renren, Wang, Yun, Xue, Jing, Su, Yajuan, Wei, Yayi, Ye, Tianchun. Flexible Hotspot Detection Based on Fully Convolutional Network With Transfer Learning. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2022, 41(11): 4626-4638, [3] Xiaojing Su, Yajuan Su. A novel contrast-aware SMO at 7nm technology node. SPIEnull. 2022, [4] 屈通, 盖天洋, 王书涵, 苏晓菁, 粟雅娟, 韦亚一. VLSI详细布线算法研究进展. 微电子学与计算机[J]. 2021, 38(11): 1-6, http://lib.cqvip.com/Qikan/Article/Detail?id=7106049230.
[5] Tianyang Gai, Ying Chen, Xiaojing Su, Yajuan Su, weiyayi. Hotspot Detection in Large Scale Layout with Proposal Sampling and Feature Parameters Optimization. Journal of Micro/Nanolithography[J]. 2021, [6] Yibo Lin, 屈通, Zongqing Lu, 粟雅娟, Yayi Wei. Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net Order Exploration in Detailed Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems[J]. 2021, [7] Su, Xiaojing, Shen, Dong, Wei, Yayi, Su, Yajuan, Dong, Lisong, Chen, Rui, Gai, Tianyang, Zhang, Libin. Projection-based high coverage fast layout decomposing algorithm of metal layer for accelerating lithography friendly design at full chip level. JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3[J]. 2021, 20(1): http://dx.doi.org/10.1117/1.JMM.20.1.013401.
[8] Su, Xiaojing, Zhang, Libin, Wei, Yayi, Chen, Rui, Su, Yajuan, Dong, Lisong, Du, Chunshan, Wan, Qijian, Hu, Xinyi, Yuan, CM, Kim, RH. Via Optimization Methodology for Enhancing Robustness of Design at 14/12nm Technology Node. DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIV[J]. 2021, 11328: [9] Su, Xiaojing, Wei, Yayi, Chen, Rui, Su, Yajuan, Dong, Lisong, Kwanc, Joe, Zhangc, Recoo, Du, Chunshan, Wan, Qijian, Hu, Xinyi, Yuan, CM, Kim, RH. Systematic DTCO Flow for Yield Improvement at 14/12nm Technology Node. DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIV[J]. 2021, 11328: [10] YingFei Wang, QingChun Zhang, Ping Li, XiaoJing Su, LiSong Dong, Rui Chen, LiBin Zhang, TianYang Gai, YaJuan Su, YaYi Wei, Tian Chun Ye. Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY[J]. 2021, 9: 6-9, https://doaj.org/article/3269a09e61a045ebb74841b3612bc1ff.
[11] Chen, Ying, Lin, Yibo, Chen, Rui, Dong, Lisong, Wu, Ruixuan, Gai, Tianyang, Ma, Le, Su, Yajuan, Wei, Yayi. EUV multilayer defect characterization via cycle-consistent learning. OPTICS EXPRESS[J]. 2020, 28(12): 18493-18506, http://dx.doi.org/10.1364/OE.394590.
[12] 杨荣强, 钱雅倩, 粟雅娟, 王颖倩, 陈睿, 陈颖, 盖天洋, 郭成, 屈通, 韦亚一. NC-FinFET器件的仿真研究. 微电子学[J]. 2020, 50(3): 410-415, http://lib.cqvip.com/Qikan/Article/Detail?id=7102277385.
[13] 粟雅娟. ＮＣ－ＦｉｎＦＥＴ器件的仿真研究. 微电子学. 2020, [14] Chen, Ying, Lin, Yibo, Gai, Tianyang, Su, Yajuan, Wei, Yayi, Pan, David Z. Semisupervised Hotspot Detection With Self-Paced Multitask Learning. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2020, 39(7): 1511-1523, http://dx.doi.org/10.1109/TCAD.2019.2912948.
[15] 粟雅娟. Design rule optimization for via layers of multiple patterning solution at 7nm technology node. Proc. SPIE. 2020, [16] 郭成, 粟雅娟, 陈睿, 董立松, 张利斌, 陈颖, 盖天洋, 韦亚一. 化学外延方式的嵌段共聚物定向自组装. 微纳电子技术[J]. 2020, 155-162, https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ&dbname=CJFDLAST2020&filename=BDTQ202002012&v=MTQyOTk4ZVgxTHV4WVM3RGgxVDNxVHJXTTFGckNVUjdxZVorZHFGQ2ptVjdySUp5bmZmN0c0SE5ITXJZOUVab1I=.
[17] 王英菲, 张青淳, 苏晓菁, 董立松, 陈睿, 张利斌, 盖天洋, 粟雅娟, 韦亚一, 叶甜春. 先进工艺下的版图邻近效应研究进展. 微电子学[J]. 2020, 50(5): 675-682, https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ&dbname=CJFDLAST2020&filename=MINI202005012&v=MTMwNTExVDNxVHJXTTFGckNVUjdxZVp1ZHVGeWpnVkwvQktDVEZaN0c0SE5ITXFvOUVab1I4ZVgxTHV4WVM3RGg=.
[18] 杨双, 石新新, 伍宏, 粟雅娟, 董立松, 陈睿, 张利斌, 苏晓菁, 陈颖, 盖天洋, 郭成, 屈通, 韦亚一. 针对更精确电迁移预测应用的热耦合模型建模. 微电子学[J]. 2020, 50(5): 732-737, http://lib.cqvip.com/Qikan/Article/Detail?id=7103260439.
[19] Chen Ying, Lin Yibo, Gai Tianyang, Su Yajuan, Wei Yayi, Pan David Z, ACM. Semi-supervised Hotspot Detection with Self-paced Multi-Task Learning. 24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019)null. 2019, 420-425, http://dx.doi.org/10.1145/3287624.3287685.
[20] Chen, Ying, Lin, Yibo, Dong, Lisong, Gai, Tianyang, Chen, Rui, Su, Yajuan, Wei, Yayi, Pan, David Z. SoulNet: ultrafast optical source optimization utilizing generative neural networks for advanced lithography. JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS[J]. 2019, 18(4): http://dx.doi.org/10.1117/1.JMM.18.4.043506.
[21] Gai Tianyang, Chen Ying, Gao Pengzheng, Su Xiaojing, Dong Lisong, Su Yajuan, Wei Yayi, Ye Tianchun, Cain JP. Sample patterns extraction from layout automatically based on hierarchical cluster algorithm for lithography process optimization. DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIIInull. 2019, 10962: [22] Su Xiaojing, Dong Lisong, Wei Yayi, Su Yajuan, Chen Rui, Du Chunshan, Cain JP. Design Rule Exploration for Width Sensitive Zone for Metal Layers in Advanced Nodes. DESIGNPROCESSTECHNOLOGYCOOPTIMIZATIONFORMANUFACTURABILITYXIIInull. 2019, 10962: [23] Su, Xiaojing, Shen, Dong, Wei, Yayi, Fan, Taian, Dong, Lisong, Zhang, Libin, Su, Yajuan, Chen, Rui, Ye, Tianchun. Probability prediction model for bridging defects induced by combined influences from lithography and etch variations. JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS[J]. 2019, 18(2): [24] 粟雅娟. Design rule exploration for width sensitive zone for metal layers in advanced nodes." Design-Process-Technology Co-optimization for Manufacturability. International Society for Optics and Photonics. 2019, [25] Su Xiaojing, Chen Rui, Wei Yayi, Su Yajuan, Dong Lisong, Rankin JH, Preil ME. A Fast DFM-Driven Standard Cell Qualification Approach for Critical Layers of 14nm Technology Node. PHOTOMASK TECHNOLOGY 2019null. 2019, 11148: [26] 盖天洋, 粟雅娟, 陈颖, 韦亚一. 基于机器学习的光刻坏点检测研究进展. 微纳电子技术[J]. 2019, 56(6): 421-428, http://lib.cqvip.com/Qikan/Article/Detail?id=7002018766.
[27] Chen Ying, Gai Tianyang, Su Xiaojing, Wei Yayi, Su Yajuan, Ye Tianchun, Cain JP, Yuan CM. Hybrid hotspot library building based on optical and geometry analysis at early stage for new node development. DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIInull. 2018, 10588: [28] Zhang, Libin, Ma, Le, Chen, Rui, He, Jianfang, Su, Xiaojing, Dong, Lisong, Su, Yajuan, Wei, Yayi. Pattern quality and defect evaluation based on cross correlation and power spectral density methods. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B[J]. 2018, 36(5): https://www.webofscience.com/wos/woscc/full-record/WOS:000444809600019.
[29] Yan, Xiangyu, Jia, Kunpeng, Su, Yajuan, Ma, Yuanjun, Luo, Jun, Zhu, Huilong, Wei, Yayi. Edge-Contact Formed by Oxygen Plasma and Rapid Thermal Annealing to Improve Metal-Graphene Contact Resistance. ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY[J]. 2018, 7(2): M11-M15, https://www.webofscience.com/wos/woscc/full-record/WOS:000425215200025.
[30] 闫祥宇, 罗军, 贾昆鹏, 粟雅娟, 战俊. 基于CVD单层MoS2 FET的光电探测器. 微纳电子技术[J]. 2017, http://159.226.55.106/handle/172511/18124.
[31] Zhao Lijun, Su Xiaojing, Su Yajuan, Wei Yayi, Ye Tianchun, Chen Ying. Enhancing manufacturability of standard cells by using DTCO methodology. 2017, http://159.226.55.106/handle/172511/18268.
[32] 战俊, 段宁远, 贾昆鹏, 罗军, 粟雅娟. 用于FET的PECVD SiNx掺杂MoS2的有效性与可控性. 微纳电子技术[J]. 2017, http://159.226.55.106/handle/172511/18122.
[33] Duan Yingli, Su Xiaojing, Chen Ying, Su Yajuan. Design technology co-optimization for 14/10nm metal1 double patterning layer. 2016, http://159.226.55.106/handle/172511/16339.
[34] 贾昆鹏, 罗军, 胡荣炎, 战俊, 曹合适, 粟雅娟, 朱慧珑, 谢玲, 赵超, 陈大鹏. Evaluation of PMMA Residues as a Function of Baking Temperature and a Graphene Heat-Free-Transfer Process to Reduce Them. ECS JOURNAL OF SOLID STATE SCIENCE AND TEHCHNOLOGY[J]. 2016, http://159.226.55.106/handle/172511/16197.
[35] Duan, Yingli, Su, Xiaojing, Chen, Ying, Su, Yajuan, Shao, Feng, Zhang, Recco, Lei, Junjiang, Wei, Yayi, Capodieci, L, Cain, JP. Design Technology Co-optimization for 14/10nm Metal1 Double Patterning Layer. DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY Xnull. 2016, 9781: http://dx.doi.org/10.1117/12.2218711.
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[53] 粟雅娟. 采用电压调度的最小化功耗算法. 电子学报英文版. 2008, [54] SU Yajuan, WEI Shaojun, YE Tianchun, CHEN Lan, LUO Jiajun. Peak Power Minimizing Algorithm by Voltage Scheduling. 电子学报：英文版[J]. 2008, 17(1): 85-89, http://lib.cqvip.com/Qikan/Article/Detail?id=27546378.
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（2） 集成电路IP核通用技术要求，参与，部委级，2011-06--2013-12
（3） 圆晶级石墨烯电子材料与器件研究，参与，国家级，2011-01--2014-12
（4） 低功耗器件建模与集成电路，主持，国家级，2010-10--2016-12
（5） DFM工具实用化及DFM建库技术，参与，国家级，2009-08--2013-12
（6） 22纳米关键工艺技术先导研究与平台建设，参与，国家级，2009-01--2013-11