基本信息
胡伟武 男 博导 计算技术研究所
电子邮件:
通信地址:北京市海淀区中关村科学院南路6号
邮政编码:100190

研究领域

计算机体系结构、集成电路设计

教育背景

   
学位
中科院计算所 1991.09--1996.03 工学博士学位

工作经历

   
工作简历

 1996.3-1997.6,中国科学院计算技术研究所,助研

1997.7-2000.2,中国科学院计算技术研究所,副研

2000.3-至今,中国科学院计算技术研究所,研究员

 

社会兼职
20080602-- 全国人大代表

教授课程

处理器设计

专利与奖励

   
奖励信息

1、“并行计算机及并行算法”,1995年,中国科学院“中科院科技进步奖”二等奖,第9完成人

2、博士学位论文“共享存储系统中的访存事件次序”,1999年,国家教育部“全国优秀博士学位论文奖”

3、“龙芯CPU”,2003年,中国科学院“中科院杰出成就奖”,排名第2

42004年,中国工程院“光华工程科技奖”青年奖

5、“龙芯2号增强型高性能通用处理器”,2006年,中国计算机学会“王选奖”一等奖,第1完成人

62006年,入选国家人事部“新世纪百千万人才工程”

72007年,中央组织部、国家人事部、中国科协“中国青年科技奖”

8、“面向计算机系统结构领域高级人才培养的课程建设”,2008年,中国科学院“中科院教学成果奖”一等奖,第1完成人

专利成果
1、20040901 动态索引的微处理器高速缓存方法 ZL01144708.7 发明
2、20040602 CPU硬件支持的系统攻击防范方法 ZL01135046 .6 发明
3、20070321 MIPS指令集的处理器扩展指令及其编码方法和部件 ZL200410039460.1  发明
4、20051228 基于操作队列复用的指令流水线系统和方法 ZL01141495.2  发明
5、20060329 一种定点除法部件中提前终止循环计算的方法 ZL03154837.7  发明
6、20070606 一种浮点除法部件中提前终止循环计算的方法及电路 ZL03155044.4 发明
7、20060826 一种减少SRT-4除法和开根部件循环次数的方法及电路 ZL03155313.3 发明
8、20080723 在微处理器用户态随机验证中实现核心态程序验证的方法 ZL200610078226.9  发明

出版信息

发表文章
1. Weiwu Hu, Ru Wang, Yunji Chen, etc. Godson-3B: A 1GHz 40W 8-Core 128GFlops Processor in 65nm CMOS. International Solid-State Circuits Conference(ISSCC’2011)
2. Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen and Weiwu hu ,Empirical Design Bugs Prediction for Verification, Design, Automation and Test in Europe(Date’2011)
3. Yunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu, LReplay: A Pending Period Based Deterministic Replay Scheme, Proc. Of 37th ACM/IEEE International Symposium on Computer Architecture(ISCA 2010) (EI)
4. Menghao Su, Yunji Chen, and Xiang Gao, A General Method to Make Multi-Clock System Deterministic, Proc. of Design, Automation, and Test in Europe (DATE'10), 2010(EI)
5. Dan Tang, Yungang Bao, Weiwu HU, Mingyu Chen, DMA Cache: Using On-Chip Storage to Architecturally Separate I/O Data from CPU Data for Improving I/O Performance, the 16th International Symposium on High Performance Computer Architecture(HPCA’10)(EI)
6. Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan. Fast Complete Memory Consistency Verification. The 15th International Symposium on High-Performance Computer Architecture (HPCA2009) (EI)
7. Weiwu Hu, Jian Wang, Xiang Gao, Yunji Chen, Qi Liu, Guojie Li,Godson-3: A Scalable Multi-core RISC Processor with X86 Emulation Support,IEEE Micro, Vol. 29, No. 2, March 2009 (EI)
8. Weiwu Hu, Qi Liu, Jian Wang, Songsong Cai,etc, Efficient Binary Translation System with Low Hardware Cost, IEEE International Conference on Computer Design, 2009(EI)
9. Weiwu Hu, Jian Wang, Xiang Gao, Yunji Chen, Micro-architecture of Godson-3 Multi-Core Processor, hot chips 2008
10. Weiwu Hu, Jian Wang, Making Effective Decisions in Computer Architects’ Real-World: Lessons and Experiences with Godson-2 Processor Designs, Journal of Computer Science and Technology, 23(4): 620-632 July 2008(SCI Index)
11. Weiwu Hu, Jiye Zhao, Shiqiang Zhong, Xu Yang, Elio Guidetti, Chris Wu, Implementing a 1GHz Four-issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology, Journal of Computer Science and Technology,22(1):1-14, January 2007(SCI Index)
12. Weiwu Hu, Rui Hou, Junhua Xiao, Longbing Zhang, High performance general-purpose microprocessors: Past and future,Journal of Computer Science and Technology, 21(5):631-640, September 2006(SCI Index)
13. 胡伟武,张福新,李祖松,龙芯2号处理器设计和性能分析,计算机研究与发展,43(6):959-966,2006(EI收录)
14. 7 Weiwu Hu, Fuxin Zhang, Zusong Li, Microarchitecture of the Godson-2 processor. Journal of Computer Science and Technology, 20(2):243-249, 2005.2.(SCI Index)
15. 胡伟武,唐志敏,龙芯1号处理器结构设计,计算机学报,2003,26(4): 385-394(EI收录)
16. Hu Weiwu, Zhang Fuxin, Liu Haiming, Dynamic data prefetching in home-based software DSMs, Journal of Computer Science and Technology, 16 (3): 231-241, 2001 (SCI收录)
17. Hu Weiwu, Zhang Fuxin, and Liu Haiming. Optimizing Home-based Software DSM Protocols, Cluster Computing, 4(3), 2001.
18. Hu Weiwu, Shi Gang, and Zhang Fuxin. Communication With Threads in Software DSMs, in Proceedings of the 2001 International Conference on Cluster Computing, Oct., 2001.
19. Hu Wei, Zhang Fuxin, Liu Haiming. A new home-based software DSM protocol for SMP clusters, EURO-PAR 2000 PARALLEL PROCESSING, PROCEEDINGS, 1900: 1132-1142 2000(SCI收录)
20. Hu, Weiwu, Li Ren, Zhang Fuxin, Shi Weisong, and Tang Zhimin. Running Real Applications in Home-Based Software DSMs, in Proceedings of HPC-Asia 2000, pp. 148-153, may 2000
21. Hu Weiwu, Shi Weisong, Tang Zhimin. Write detection in home-based software DSMs,EURO-PAR’99, PARALLEL PROCESSING, 1685: 909-913 1999(SCI收录、ISTP收录)
22. Hu Weiwu, Shi Weisong, Tang Zhimin. JIAJIA: A software DSM system based on a new cache coherence protocol, HIGH-PERFORMANCE COMPUTING AND NETWORKING, PROCEEDINGS, 1593: 463-472,1999(SCI收录)
23. 胡伟武,施巍松,唐志敏,基于新型Cache一致性协议的共享虚拟存储系统,计算机学报,1999, 20(5): 467-475 (EI收录)
24. Hu Weiwu,Shi Weisong, Tang Zhimin. Adaptive write detection in home-based software DSMs, In: Proc. of IEEE International Symposium on High Performance Distributed Computing, 1999, 353-354(EI收录)
25. Hu Weiwu, Shi Weisong, Tang Zhimin. Reducing system overheads in home-based software DSMs, In : Proc. of the International Parallel Processing Symposium, IPPS, 1999, 167-173(EI收录、ISTP收录)
26. Hu Weiwu, Shi Weisong, and Tang Zhimin. Home Migration in Home-Based Software DSMs, in Proceedings of the 1st Workshop of the Software Distributed Shared Memory, pp. 21-26, Rhodes, June, 1999
27. Hu Weiwu, Reducing Message Overhead in Home-Based Software DSMs, in Proceedings of the 1st Workshop of the Software Distributed Shared Memory, pp. 7-11, Rhodes, June, 1999.
28. Hu Weiwu, Shi Weisong, Tang Zhimin, Li Ming, Lock-based cache coherence protocol for scope consistency, Journal of Computer Science and Technology, 13(2): 97-109, 1998(EI收录)
29. Hu Weiwu, Shi Weisong, Tang Zhimin. Framework of memory consistency models, Journal of Computer Science and Technology, 13(2):110-124, 1998(EI收录)
30. Hu Weiwu, Xia Peisu. Out-of-order execution in sequentially consistent shared-memory systems: theory and experiments, Journal of Computer Science and Technology, 13(2):125-139, 1998(EI收录)
31. Hu Weiwu, Xia Peisu. Hardware-controlled prefetching in directory-based cache coherent systems, In: Proc. of Frontiers of Massively Parallel Computation, 1996, 206-213(EI收录、ISTP收录)
32. Hu Weiwu, Xia, Peisu. event ordering condition for correct executions in shared-memory systems, In: Proc. of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN, 1996, 84-89(EI收录、ISTP收录)
33. Hu Weiwu, Improving the Performance of Sequential Consistency in Cache Coherence Systems, In Proceedings of the 1995 International Conference on High Performance Computing, pp. 81-86, New Delhi, Dec. 1995
34. Hu Weiwu. Graph model for investigating memory consistency, In: Proc. of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS, 1994, p 516-523(EI收录)
35. Weiwu Hu and Zhimin Tang, A Maximum Time Difference Pipelined Multiplier, In Proceedings of the first International Conference on ASIC,pp.360-365, Beijing, Oct.1994
36. 张福新,章隆兵,胡伟武,唐志敏,可恢复的软件DSM系统JIACKPT,软件学报, 16(2):165-173, 2005.2(EI收录)
37. Zhang Ge, Qi Zichu, Hu Weiwu. A Novel Design of Leading Zero Anticipation Circuit With Parallel Error Detection. IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005.05, pp.676-679 Vol. 1.
38. Hou Rui, Zhang Fuxin, Hu Weiwu. A Memory Bandwidth Effective Cache Store Miss Policy. In: Proc. of the 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC’2005), October, 2005(SCI收录)
39. 吴少刚,章隆兵,蔡飞,胡伟武, 一种适用于机群OpenMP系统的有效调度算法, 计算机研究与发展,41(7):1298-1305,2004年7月(EI收录)
40. 章隆兵,吴少刚,蔡飞,胡伟武, 适合机群OpenMP系统的制导扩展, 计算机学报,27(8):1129-1136,2004年8月(EI收录)
41. 章隆兵,吴少刚,蔡飞,胡伟武, PC机群上共享存储与消息传递的比较,软件学报,15(6):842-849,2004年6月(EI收录)
42. Liu Haiming, Hu Weiwu. A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM, In: Proc. of IPDPS 2001,2001
43. 唐志敏,施巍松,胡伟武,曙光1000A上消息传递与共享存储的比较, 计算机学报,23(2):134-140, 2000(EI收录)
44. Shi Weisong, Hu Weiwu, Tang Zhimin. Where does the time go in software DSMs? - experiences with JIAJIA, Journal of Computer Science and Technology, 14(3):193-205, 1999 (EI收录)
45. Eskicioglu M. Rasit,Marsland T. Anthony,Hu Weiwu,Shi Weisong. Evaluation of the JIAJIA software DSM system on high performance computer architectures, In: Proc. of the Hawaii International Conference on System Sciences, 1999, 287 (EI收录)
46. Shi Weisong, Hu Weiwu, Tang Zhimin, Eskicioglu M. Rasit. Dynamic task migration in home-based software DSM systems, In: Proc. of IEEE International Symposium on High Performance Distributed Computing, 1999, 339-340 (EI收录)
47. Shi Weisong, Hu Weiwu, Tang Zhimin. An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems, Operating Systems Review (ACM), 31(4):41-54, 1997 (EI收录)
48. Shi Weisong, Hu Weiwu, etc. An Innovative Implementation for Directory-based Cache Coherence in Shared Memory Multiprocessors, Computer Architecture News, 25(5):2-, 1997, (EI收录)
49. Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu, Processor Directed Dynamic Page Policy, 11th Asia-Pacific Computer System Architecture Conference (ACSAC2006) pp.109-122. (SCI收录)
50. Zusong Li, Xianchao Xu, Weiwu Hu, and Zhimin Tang. Microarchitecture and Performance Analysis of Godson-2 SMT Processor. Proceedings of the 24th International Conference on Computer Design (ICCD), San Jose, California, USA, October 2-4, 2006, pp. 485-490(EI收录)
51. Rui Hou, Longbing Zhang, Weiwu Hu. A hybrid hardware/software generated prefetching thread mechanism on chip multiprocessors. In: Proceeding of 12th Euro-Par Parallel Processing Conference, 2006, 506-516(SCI收录)
52. Ge Zhang, Weiwu Hu, Zichu Qi, Parallel error detection for leading zero anticipation, Journal of Computer Science and Technology,21(6):901-906,2006(SCI收录)
53. 张戈,齐子初,胡伟武,龙芯2号处理器功能部件设计,计算机研究与发展,43(6):967-973(EI收录)
54. 陈云霁,马麟,沈海华,胡伟武,龙芯2浮点除法运算电路形式验证,计算机研究与发展,43(10):1835-1841, 2006(EI收录)

出版著作
1. 共享存储系统结构 高等教育出版社 20010701 ISBN 7-04-009849-0
2. 计算机体系结构 清华大学出版社 20110601 ISBN 978-7-302-25689-2
科研项目
1. 高性能多核高性能多核CPU研发与应用,国家“核高基”科技重大专项,执行时间:2009.01-2011.12
2. 四核龙芯通用CPU研制,国家863重点项目,负责人,执行时间:2008.1-2010.12
3. 高性能多核CPU结构设计及原型系统研究,中科院知识创新工程重要方向项目,负责人,执行时间:2007.1-2007.12
4. 计算机系统结构,国家杰出青年基金项目,负责人,执行时间:2004.1-2007.12
5. 龙芯2号增强型处理器芯片设计,国家863项目,负责人,执行时间:2005.5-2005.12
6. 高性能通用CPU芯片全定制实现及系统集成,国家863项目,负责人,执行时间:2002.10-2004.6
7. 共享存储机群系统中关键技术研究,国家自然科学基金面上项目,负责人,执行时间:2002.8-2003.12

指导学生

蔡晔  博士研究生  081201-计算机系统结构  80132-计算技术研究所

蔡飞  博士研究生  081201-计算机系统结构  80132-计算技术研究所

范宝峡  博士研究生  081201-计算机系统结构  80132-计算技术研究所

陈博文  博士研究生  081201-计算机系统结构  80132-计算技术研究所

叶笑春  博士研究生  081201-计算机系统结构  80132-计算技术研究所

杨梁  博士研究生  081201-计算机系统结构  80132-计算技术研究所

齐子初  博士研究生  081201-计算机系统结构  80132-计算技术研究所

于航  硕士研究生  081201-计算机系统结构  80132-计算技术研究所

刘宏伟  硕士研究生  081201-计算机系统结构  80132-计算技术研究所

苏孟豪  博士研究生  081201-计算机系统结构  80132-计算技术研究所

汪文祥  博士研究生  081201-计算机系统结构  80132-计算技术研究所

刘奇  博士研究生  081201-计算机系统结构  80132-计算技术研究所

王焕东  博士研究生  081201-计算机系统结构  80132-计算技术研究所

段玮  博士研究生  081201-计算机系统结构  80132-计算技术研究所

王茹  博士研究生  081201-计算机系统结构  80132-计算技术研究所

钱诚  博士研究生  081201-计算机系统结构  80132-计算技术研究所

陈帅  硕士研究生  081201-计算机系统结构  80132-计算技术研究所

蔡嵩松  博士研究生  081201-计算机系统结构  80132-计算技术研究所

李晓钰  博士研究生  081201-计算机系统结构  80132-计算技术研究所

尹文轩  博士研究生  081201-计算机系统结构  80132-计算技术研究所

郝守青  博士研究生  081201-计算机系统结构  80132-计算技术研究所

张晓辉  博士研究生  081201-计算机系统结构  80132-计算技术研究所

肖斌  博士研究生  081201-计算机系统结构  80132-计算技术研究所

招生信息

   
招生专业
081201-计算机系统结构
081203-计算机应用技术

出版信息

   
发表论文
[1] 胡伟武, 汪文祥, 吴瑞阳, 王焕东, 曾露, 徐成华, 高翔, 张福新. 龙芯指令系统架构技术. 计算机研究与发展[J]. 2023, 60(1): 2-16, http://lib.cqvip.com/Qikan/Article/Detail?id=7108741859.
[2] 胡伟武. 龙芯指令系统架构技术. 计算机研究与发展[J]. 2022, https://kns.cnki.net/kcms/detail/11.1777.tp.20220707.1530.008.html.
[3] 胡伟武. “芯芯”之火,可以燎原. 中国科技财富[J]. 2021, 49-50, http://lib.cqvip.com/Qikan/Article/Detail?id=7104268454.
[4] 胡伟武, 曹永胜. 想靠外国帮我们建立自主可控的信息产业体系不可取. 中国军转民[J]. 2020, 8-13, http://lib.cqvip.com/Qikan/Article/Detail?id=7101938851.
[5] 胡伟武. 发展自主CPU应该走市场带技术的道路. 信息安全研究[J]. 2019, 5(5): 450-453, http://lib.cqvip.com/Qikan/Article/Detail?id=7001750964.
[6] 胡伟武. 核心技术需要在试错中发展. 中国科学:信息科学[J]. 2018, 48(8): 1097-1101, http://lib.cqvip.com/Qikan/Article/Detail?id=676082930.
[7] 胡伟武. 自主可控CPU“三要素”. 信息安全研究[J]. 2018, 4(5): 412-414, http://lib.cqvip.com/Qikan/Article/Detail?id=675101164.
[8] 靳国杰, 张戈, 高翔, 胡伟武. 龙芯信息化平台的应用迁移工作思考. 网络空间安全[J]. 2018, 9(9): 10-15, http://lib.cqvip.com/Qikan/Article/Detail?id=7001156020.
[9] 胡伟武. 造就中国自主CPU“最强大脑”. 紫光阁[J]. 2017, 51-52, http://lib.cqvip.com/Qikan/Article/Detail?id=671543868.
[10] Hu, Weiwu, Zhang, Yifu, Fu, Jie. An introduction to CPU and DSP design in China. SCIENCE CHINA-INFORMATION SCIENCES[J]. 2016, 59(1): https://www.webofscience.com/wos/woscc/full-record/WOS:000368314000006.
[11] Hu, Weiwu, Zhang, Yifu, Fu, Jie. An introduction to CPU and DSP design in China. SCIENCE CHINA-INFORMATION SCIENCES[J]. 2016, 59(1): https://www.webofscience.com/wos/woscc/full-record/WOS:000368314000006.
[12] 胡伟武, 靳国杰, 汪文祥, 张晓春, 王焕东. 龙芯指令系统融合技术. 中国科学. 信息科学[J]. 2015, 45(4): 459-479, https://www.sciengine.com/doi/10.1360/N112014-00300.
[13] 胡伟武, 梁华岳. 基于HT的光互连接口的设计. 高技术通讯[J]. 2015, 1005-1010, http://lib.cqvip.com/Qikan/Article/Detail?id=668281314.
[14] 梁华岳, 胡伟武. 一种用HT协议实现光纤传输的数据转换结构. 高技术通讯[J]. 2015, 561-566, http://lib.cqvip.com/Qikan/Article/Detail?id=666426463.
[15] Zhang Xiaochun, Guo Qi, Chen Yunji, Chen Tianshi, Hu Weiwu, IEEE. HERMES: A Fast Cross-ISA Binary Translator with Post-Optimization. 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION (CGO)null. 2015, 246-256, [16] 吴瑞阳, 汪文祥, 王焕东, 胡伟武. 龙芯GS464E处理器核架构设计. 中国科学. 信息科学[J]. 2015, 45(4): 480-500, https://www.sciengine.com/doi/10.1360/N112014-00292.
[17] Liu ShaoLi, Li Ling, Chen YunJi, Hu WeiWu. Auxiliary stream for optimizing memory access of video decoders. SCIENCE CHINA-INFORMATION SCIENCES[J]. 2014, 57(1): https://www.webofscience.com/wos/woscc/full-record/WOS:000332596000003.
[18] Guo, Qi, Chen, Tianshi, Chen, Yunji, Wang, Rui, Chen, Huanhuan, Hu, Weiwu, Chen, Guoliang. Pre-Silicon Bug Forecast. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS[J]. 2014, 33(3): 451-463, http://dx.doi.org/10.1109/TCAD.2013.2288688.
[19] Hu, Weiwu, Yang, Liang, Fan, Baoxia, Wang, Huandong, Chen, Yunji. An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS[J]. 2014, 49(1): 41-49, https://www.webofscience.com/wos/woscc/full-record/WOS:000329052700005.
[20] Liu ShaoLi, Li Ling, Chen YunJi, Hu WeiWu. Auxiliary stream for optimizing memory access of video decoders. SCIENCE CHINA-INFORMATION SCIENCES[J]. 2014, 57(1): https://www.webofscience.com/wos/woscc/full-record/WOS:000332596000003.
[21] Chen, Yunji, Chen, Tianshi, Li, Ling, Li, Lei, Yang, Liang, Su, Menghao, Hu, Weiwu. LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging. IEEE TRANSACTIONS ON COMPUTERS[J]. 2013, 62(9): 1732-1744, https://www.webofscience.com/wos/woscc/full-record/WOS:000322453200005.
[22] Hu Weiwu, Zhang Yifu, Yang Liang, Fan Baoxia, Chen Yunji, Zhong Shiqiang, Wang Huandong, Qi Zichu, Wang Pengyu, Gao Xiang, Yang Xu, Xiao Bin, Wang Hongsheng, Yang Zongren, Yang Liqiong, Chen Shuai, IEEE. Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-Core Processor. 2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)null. 2013, 56: 54-U1274, [23] Chen, Yunji, Chen, Tianshi, Li, Ling, Wu, Ruiyang, Liu, Daofu, Hu, Weiwu. Deterministic Replay Using Global Clock. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION[J]. 2013, 10(1): https://www.webofscience.com/wos/woscc/full-record/WOS:000317426900001.
[24] Guo, Qi, Chen, Tianshi, Chen, Yunji, Li, Ling, Hu, Weiwu. Microarchitectural design space exploration made fast. MICROPROCESSORS AND MICROSYSTEMS[J]. 2013, 37(1): 41-51, http://dx.doi.org/10.1016/j.micpro.2012.07.006.
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[27] Hu, WeiWu, Gao, YanPing, Chen, TianShi, Xiao, JunHua. The Godson Processors: Its Research, Development, and Contributions. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY[J]. 2011, 26(3): 363-372, http://lib.cqvip.com/Qikan/Article/Detail?id=37759965.
[28] 王茹, 范宝峡, 杨梁, 高燕萍, 刘动, 肖斌, 王江嵋, 张译夫, 王宏, 胡伟武. Physical Implementation of the Eight-Core Godson-3B Microprocessor. 计算机科学技术学报:英文版[J]. 2011, 26(3): 520-527, http://lib.cqvip.com/Qikan/Article/Detail?id=37759977.
[29] Wang, Ru, Fan, BaoXia, Yang, Liang, Gao, YanPing, Liu, Dong, Xiao, Bin, Wang, JiangMei, Zhang, YiFu, Wang, Hong, Hu, WeiWu. Physical Implementation of the Eight-Core Godson-3B Microprocessor. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY[J]. 2011, 26(3): 520-527, http://lib.cqvip.com/Qikan/Article/Detail?id=37759977.
[30] Hu Weiwu. Godson-3B: A 1GHz 40W 8-Core 128GFlops Processor in 65nm CMOS. PROCOFIEEEINTERNATIONALSOLIDSTATECIRCUITSCONFERENCEISSCC. 2011, [31] Bai, Rui, Wang, Jingguang, Xia, Lingli, Zhang, Feng, Yang, Zongren, Hu, Weiwu, Chiang, Patrick. Sinusoidal Clock Sampling for Multigigahertz ADCs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS[J]. 2011, 58(12): 2808-2815, https://www.webofscience.com/wos/woscc/full-record/WOS:000297632900002.
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[33] 齐子初, 刘慧, 李向库, 胡伟武. Design for Testability Features of Godson-3 Multicore Microprocessor. 计算机科学技术学报:英文版[J]. 2011, 26(2): 302-313, http://lib.cqvip.com/Qikan/Article/Detail?id=36950048.
[34] 朱海涛, 陈云霁, 钱诚, 王玲, 胡伟武. 基于向量扩展多核处理器的矩阵乘法算法优化研究. 中国科学技术大学学报[J]. 2011, 41(2): 173-182, http://lib.cqvip.com/Qikan/Article/Detail?id=37034248.
[35] 杨旭, 刘江, 钱诚, 苏孟豪, 吴瑞阳, 陈云霁, 胡伟武. 一种面向多核处理器的通用可调试性架构. 计算机辅助设计与图形学学报[J]. 2011, 23(10): 1656-1664, http://lib.cqvip.com/Qikan/Article/Detail?id=39439243.
[36] Qi Zichu, Guo Qi, Zhang Ge, Li Xiangku, Hu Weiwu, IEEE. Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power. 23RD INTERNATIONAL CONFERENCE ON VLSI DESIGNnull. 2010, 206-211, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000283803200035.
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[38] Xu Jun, Zhang Ge, Hu Weiwu, IEEE. Optimizing Power and Throughput for M-Out-Of-N Encoded Asynchronous Circuits. PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010)null. 2010, 151-157, [39] Chen Yunji, Hu Weiwu, Chen Tianshi, Wu Ruiyang, ACM. LReplay: A Pending Period Based Deterministic Replay Scheme. ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTUREnull. 2010, 187-197, [40] 高翔, 陈云霁, 王焕东, 唐丹, 胡伟武. System Architecture of Godson-3 Multi-Core Processors. 计算机科学技术学报:英文版[J]. 2010, 181-191, http://lib.cqvip.com/Qikan/Article/Detail?id=33054254.
[41] 高茁, 杨宗仁, 赵莹, 杨袆, 张璐, 黄令仪, 胡伟武. A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner. 半导体学报[J]. 2009, 106-112, http://lib.cqvip.com/Qikan/Article/Detail?id=30061472.
[42] 高茁, 杨袆, 钟石强, 杨旭, 黄令仪, 胡伟武. A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS. 半导体学报[J]. 2009, 015004-1, http://lib.cqvip.com/Qikan/Article/Detail?id=29407930.
[43] 胡伟武. 2020年“中国芯”支撑信息产业发展. 中国科技投资[J]. 2009, 59-60, http://lib.cqvip.com/Qikan/Article/Detail?id=32397625.
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[45] 杨祎, 高茁, 杨丽琼, 黄令仪, 胡伟武. Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process. 半导体学报[J]. 2009, 015001-1, http://lib.cqvip.com/Qikan/Article/Detail?id=29407927.
[46] 李祖松, 许先超, 胡伟武, 唐志敏. 龙芯2号处理器的同时多线程设计. 计算机学报[J]. 2009, 2265-2273, http://lib.cqvip.com/Qikan/Article/Detail?id=32080316.
[47] Hu Weiwu, Liu Qi, Wang Jian, Cai Songsong, Su Menghao, Li Xiaoyu, IEEE. Efficient Binary Translation System with Low Hardware Cost. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGNnull. 2009, 305-312, [48] 张戈, 胡伟武, 黄琨, 曾洪博, 王君. 片上多核处理器的结构级功耗建模与优化技术研究. 自然科学进展[J]. 2009, 19(12): 1398-1409, http://lib.cqvip.com/Qikan/Article/Detail?id=32392913.
[49] Hu, Weiwu, Wang, Jian, Gao, Xiang, Chen, Yunji, Liu, Qi, Li, Guojie. GODSON-3: A SCALABLE MULTICORE RISC PROCESSOR WITH X86 EMULATION. IEEE MICRO[J]. 2009, 29(2): 17-29, https://www.webofscience.com/wos/woscc/full-record/WOS:000264804100004.
[50] Chen Yunji, Lv Yi, Hu Weiwu, Chen Tianshi, Shen Haihua, Wang Pengyu, Pan Hong, IEEE Comp Soc. Fast Complete Memory Consistency Verification. HPCA-15 2009: FIFTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGSnull. 2009, 381-+, [51] Gao Zhuo, Yang Zongren, Zhao Ying, Yang Yi, Zhang Lu, Huang Lingyi, Hu Weiwu. A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner. JOURNAL OF SEMICONDUCTORS[J]. 2009, 104-110, http://lib.cqvip.com/Qikan/Article/Detail?id=30061472.
[52] Zhang Ge, Hu Weiwu, IEEE. An Efficient Methodology for Power Modeling and Simulation of Modern Cell-Based Microprocessors. 2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2null. 2009, 1126-+, [53] 胡伟武. 龙芯3号:具有X86翻译硬件支持的可扩展多核RISC处理器. IEEE Micro. 2009, [54] Zhuo Gao, Kesharwani Divya, Chiang Patrick, Hu Weiwu, IEEE. Measuring and Compensating for Process Mismatch-Induced, Reference Spurs in Phase-Locked Loops Using a Sub-Sampled DSP. ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5null. 2009, 1585-+, http://apps.webofknowledge.com/CitedFullRecord.do?product=UA&colName=WOS&SID=5CCFccWmJJRAuMzNPjj&search_mode=CitedFullRecord&isickref=WOS:000275929801077.
[55] 李祖松, 郇丹丹, 胡伟武, 唐志敏. Chip Multithreaded Consistency Model. 计算机科学技术学报:英文版[J]. 2008, 23(2): 298-封3, http://lib.cqvip.com/Qikan/Article/Detail?id=26568589.
[56] Zhang Feng, Yang Zongren, Feng Wei, Cui Hao, Huang Lingyi, Hu Weiwu, Osseiran A, Renovell M, Amira A, Pun KP, Leung LLK. A high speed CMOS transmitter and rail-to-rail receiver. DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGSnull. 2008, 67-70, http://dx.doi.org/10.1109/DELTA.2008.32.
[57] 冯子军, 肖俊华, 胡伟武. 龙芯1号IP验证方法. 计算机工程[J]. 2008, 34(5): 31-32,35, http://lib.cqvip.com/Qikan/Article/Detail?id=26781798.
[58] 邹琼, 伍鸣, 胡伟武, 章隆兵. 基于插桩分析的Java虚拟机自适应预取优化框架. 软件学报[J]. 2008, 19(7): 1581-1589, http://lib.cqvip.com/Qikan/Article/Detail?id=27587619.
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[60] Fan, Qifei, Zhang, Ge, Hu, Weiwu, IEEE. A synchronized variable frequency clock scheme in chip multiprocessors. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10null. 2008, 3410-+, [61] 王焕东, 高翔, 陈云霁, 胡伟武. 龙芯3号互联系统的设计与实现. 计算机研究与发展[J]. 2008, 45(12): 2001-2010, http://lib.cqvip.com/Qikan/Article/Detail?id=28875848.
[62] 张仕健, 许彤, 章隆兵, 胡伟武. 一个基于微处理器功能模型的可靠度评估系统. 计算机学报[J]. 2008, 31(3): 391-399, http://lib.cqvip.com/Qikan/Article/Detail?id=26765971.
[63] 张锋, 冯伟, 崔浩, 杨袆, 黄令仪, 胡伟武. 一个0.18μm高速低功耗的发送和接收电路. 半导体学报[J]. 2008, 29(5): 836-840, http://lib.cqvip.com/Qikan/Article/Detail?id=27252565.
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[65] 杨袆, 杨丽琼, 张锋, 高茁, 黄令仪, 胡伟武. 一个用于高速信号传输的对PVT变化不敏感的低功耗锁相环. 半导体学报[J]. 2008, 29(10): 1873-1878, http://lib.cqvip.com/Qikan/Article/Detail?id=28463801.
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[69] 高翔, 章隆兵, 胡伟武. 一种基于容量复用的异构CMP Cache. 计算机研究与发展[J]. 2008, 45(5): 877-885, http://lib.cqvip.com/Qikan/Article/Detail?id=27154140.
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[72] 李祖松, 许先超, 胡伟武, 唐志敏. 龙芯2号同时多线程处理器的软硬件接口设计. 软件学报[J]. 2007, 18(7): 1806-1817, http://lib.cqvip.com/Qikan/Article/Detail?id=24884690.
[73] 郇丹丹, 李祖松, 胡伟武, 刘志勇. 结合访存失效队列状态的预取策略. 计算机学报[J]. 2007, 30(7): 1104-1114, http://lib.cqvip.com/Qikan/Article/Detail?id=25176122.
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[95] 陈云霁, 马麟, 沈海华, 胡伟武. 龙芯2号微处理器浮点除法功能部件的形式验证. 计算机研究与发展[J]. 2006, 43(10): 1835-1841, https://crad.ict.ac.cn/cn/article/id/1969.
[96] Zhang, Ge, Hu, WeiWu, Qi, ZiChu. Parallel error detection for leading zero anticipation. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY[J]. 2006, 21(6): 901-906, http://www.corc.org.cn/handle/1471x/2378448.
[97] 胡伟武, 张福新, 李祖松. 龙芯2号处理器设计和性能分析. 计算机研究与发展[J]. 2006, 43(6): 959-966, http://lib.cqvip.com/Qikan/Article/Detail?id=22033329.
[98] 张戈, 齐子初, 胡伟武. 龙芯2号处理器功能部件设计. 计算机研究与发展[J]. 2006, 43(6): 967-973, http://lib.cqvip.com/Qikan/Article/Detail?id=22033330.
[99] 胡伟武. 为了龙芯的跳动. 中国高新区[J]. 2006, 30-33, http://lib.cqvip.com/Qikan/Article/Detail?id=22614431.
[100] 张戈, 胡伟武. 高性能通用处理器中的漏电功耗优化. 计算机学报[J]. 2006, 29(10): 1764-1771, https://d.wanfangdata.com.cn/periodical/jsjxb200610005.
[101] 张福新, 章隆兵, 胡伟武, 唐志敏. 可恢复的软件DSM系统JIACKPT. 软件学报[J]. 2005, 16(2): 165-173, http://lib.cqvip.com/Qikan/Article/Detail?id=12025518.
[102] 吴少刚, 章隆兵, 蔡飞, 胡伟武. 一种适用于机群OpenMP系统的有效调度算法. 计算机研究与发展[J]. 2004, 41(7): 1298-1305, http://lib.cqvip.com/Qikan/Article/Detail?id=10343425.
[103] 刘华平, 齐子初, 胡伟武. 能使SRT算法实现的定点除法部件减少循环次数的方法. 科技开发动态[J]. 2004, 45-45, http://lib.cqvip.com/Qikan/Article/Detail?id=11192238.
[104] 刘华平, 胡伟武. 定点除法部件中提前终止循环计算的方法. 科技开发动态[J]. 2004, 45-45, http://lib.cqvip.com/Qikan/Article/Detail?id=11192237.
[105] 池天河, 张新, 韩承德, 胡伟武, 方金云. 基于并行计算的洪水灾害快速评估系统研究. 人民长江[J]. 2004, 35(5): 21-23, http://lib.cqvip.com/Qikan/Article/Detail?id=9646517.
[106] 章隆兵, 吴少刚, 蔡飞, 胡伟武. PC机群上共享存储与消息传递的比较. 软件学报[J]. 2004, 15(6): 842-849, http://lib.cqvip.com/Qikan/Article/Detail?id=10337504.
[107] 陈守顺, 黄令仪, 蒋见花, 胡伟武. 深亚微米VLSI设计中的Crosstalk问题分析及消除. 电子与封装[J]. 2004, 4(3): 48-50, http://lib.cqvip.com/Qikan/Article/Detail?id=9982295.
[108] 章隆兵, 吴少刚, 蔡飞, 胡伟武. 适合机群OpenMP系统的制导扩展. 计算机学报[J]. 2004, 27(8): 1129-1136, http://lib.cqvip.com/Qikan/Article/Detail?id=10362232.
[109] 史岗, 尹宏达, 胡明昌, 胡伟武. VIA(Virtual Interface Architecture)上的软件DSM系统实现和性能. 计算机学报[J]. 2003, 26(12): 1621-1628, http://lib.cqvip.com/Qikan/Article/Detail?id=8809564.
[110] 刘华平, 胡伟武. 一种减小SRT浮点算法时延的优化方法. 计算机研究与发展[J]. 2003, 40(11): 1650-1656, http://lib.cqvip.com/Qikan/Article/Detail?id=8609032.
[111] 史岗, 张福新, 胡伟武, 韩承德. 软件DSM机群上并行大规模地理图像处理系统ParGIP. 计算机研究与发展[J]. 2003, 40(1): 53-59, http://lib.cqvip.com/Qikan/Article/Detail?id=7384592.
[112] 唐志敏, 胡明昌, 史岗, 胡伟武. 通信对机群并行计算性能的影响. 小型微型计算机系统[J]. 2003, 24(9): 1569-1573, http://lib.cqvip.com/Qikan/Article/Detail?id=8239140.
[113] 胡伟武, 唐志敏. 龙芯1号处理器结构设计. 计算机学报[J]. 2003, 26(4): 385-396, http://lib.cqvip.com/Qikan/Article/Detail?id=7752443.
[114] 胡伟武. 博士生创新能力培养点滴. 中国研究生[J]. 2003, 10-11, http://lib.cqvip.com/Qikan/Article/Detail?id=8019284.
[115] 胡明昌, 史岗, 胡伟武, 唐志敏, 张福新. PC机群上JIAJIA与MPI的比较. 软件学报[J]. 2003, 14(7): 1187-1194, http://lib.cqvip.com/Qikan/Article/Detail?id=8049443.
[116] 戴华东, 杨学军. DSM系统中存储一致性模型的一种新框架——S^3C框架. 计算机学报[J]. 2002, 25(12): 1387-1396, http://lib.cqvip.com/Qikan/Article/Detail?id=7153805.
[117] 史岗, 张福新, 池天河, 胡伟武, 方金云, 何建邦. 地理数字图像机群并行处理试验. 计算机科学[J]. 2001, 28(5): 99-100, http://lib.cqvip.com/Qikan/Article/Detail?id=5242408.
[118] 唐志敏, 施巍松, 胡伟武. 曙光1000A上消息传递与共享存储的比较. 计算机学报[J]. 2000, 23(2): 134-, http://lib.cqvip.com/Qikan/Article/Detail?id=4138437.
[119] 方金云, 何建邦, 池天河, 胡伟武, 史岗, 张福新. 可扩展的并行地理图像处理系统. 地球信息科学[J]. 2000, 62-66, http://lib.cqvip.com/Qikan/Article/Detail?id=1001070476.
[120] 胡伟武, 唐志敏, 施巍松. Where Does the Time Go in Software DSMs?——Experiences with JIAJIA. 计算机科学技术学报:英文版[J]. 1999, 14(3): 193-, http://lib.cqvip.com/Qikan/Article/Detail?id=6795666.
[121] 唐志敏, 施巍松, 胡伟武. 基于新型Cache一致性协议的共享虚拟存储系统. 计算机学报[J]. 1999, 22(5): 467-, http://lib.cqvip.com/Qikan/Article/Detail?id=3545773.
[122] 胡伟武, 施巍松, 唐志敏. A Framework of Memory Consistency Models. 计算机科学技术学报:英文版[J]. 1998, 13(2): 110-, http://lib.cqvip.com/Qikan/Article/Detail?id=6795244.
[123] 胡伟武, 唐志敏, 李明, 施巍松. A Lock—Based Cache Coherence Protocol for Scope Consistency. 计算机科学技术学报:英文版[J]. 1998, 13(2): 97-, http://lib.cqvip.com/Qikan/Article/Detail?id=6795243.
[124] 胡伟武, 夏培肃. 顺序一致共享存储系统中的JZ乱序执行技术??模拟实现. 计算机学报[J]. 1997, 20(6): 491-, http://sciencechina.cn/gw.jsp?action=detail.jsp&internal_id=940660&detailType=1.
[125] 胡伟武, 夏培肃. 顺序一致共享存储系统中的乱序执行技术——基本理论. 计算机学报[J]. 1997, 20(6): 481-490, http://lib.cqvip.com/Qikan/Article/Detail?id=2477132.
[126] 夏培肃, 胡伟武. 顺序一致共享存储系统中的乱序执行技术——模拟实现. 计算机学报[J]. 1997, 20(6): 481-, http://lib.cqvip.com/Qikan/Article/Detail?id=2477133.
发表著作
(1) 计算机体系结构,computer architecture,清华大学出版社,2011-06,第1作者
(2) 共享存储系统结构,Shared Memory Architecture,高等教育出版社,2001-07

科研活动

   
参与会议
(1) 国际计算机体系结构大会,2008-06