基本信息
刘成  男  硕导  中国科学院计算技术研究所
电子邮件: liucheng@ict.ac.cn
通信地址: 中科院计算所
邮政编码:

研究领域

专用硬件加速,FPGA可重构计算,容错计算

招生信息

硕导

招生专业
081201-计算机系统结构
招生方向
专用硬件加速,FPGA可重构计算,容错计算

教育背景

2009-09--2016-04   香港大学   博士
2007-09--2009-07   哈尔滨工业大学   硕士
2003-09--2007-07   哈尔滨工业大学   本科

工作经历

   
工作简历
2018-06~现在, 中国科学院计算技术研究所, 副研
2016-12~2018-06,新加坡国立大学, Research Fellow

出版信息

   
发表论文
(1) Statistical Modeling of Soft Error Influence on Neural Networks, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023, 通讯作者
(2) Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses, ACM TODAES, 2023, 通讯作者
(3) Fault-Tolerant Deep Learning: A Hierarchical Perspective, The 40th IEEE VLSI Test Symposium (VTS), 2022, 第 1 作者
(4) Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception, In proceedings of ACM/IEEE Design Automation Conference (DAC), 2022, 第 5 作者
(5) On-line Fault Protection for ReRAM-based Neural Networks, IEEE Transactions on Computers, 2022, 第 3 作者
(6) A Framework for Neural Network Architecture and Compiler Co-Optimization, ACM Transactions on Embedded Computing Systems (TECS), 2022, 第 5 作者
(7) Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems, JOURNAL OF SYSTEMS ARCHITECTURE, 2022, 第 3 作者
(8) Winograd Convolution: A Perspective from Fault Tolerance, IN PROCEEDINGS OF ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC),, 2022, 通讯作者
(9) VStore: In-Storage Graph Based Vector Search Accelerator, ACM/IEEE Design Automation Conference (DAC), 2022, 第 4 作者
(10) TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning, In proceedings of ACM/IEEE Design Automation Conference (DAC), 2021, 第 3 作者
(11) EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks, IEEE TRANSACTIONS ON COMPUTERS, 2021, 第 3 作者
(12) CHaNAS: Coordinated Search for Network Architecture and Scheduling Policy, Language, Compilers, Tools and Theory of Embedded Systems (LCTES), 2021, 第 5 作者
(13) HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (TCAD), 2021, 第 1 作者
(14) GLIST: Towards In-Storage Graph Learning, USENIX Annual Technical Conference (ATC), 2021, 通讯作者
(15) Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 通讯作者
(16) R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 通讯作者
(17) Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization, proceedings of ACM/IEEE Design Automation Conference (DAC), 2021, 第 3 作者
(18) NASA: Accelerating Neural Network Design with a NAS Processor, International Symposium on Computer Architecture (ISCA), 2021, 第 4 作者
(19) PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices, The 2021 IEEE International Conference on Robotics and Automation (ICRA), 2021, 通讯作者
(20) Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2021, 第 5 作者
(21) GCiM: A Near-Data Processing Accelerator for Graph Construction, IEEE/ACM Proceedings of Design, Automation Conference (DAC), 2021, 第 2 作者
(22) Accelerating Generative Neural Networks on Unmodified Deep Learning Processors-A Software Approach, IEEE TRANSACTIONS ON COMPUTERS, 2020, 第 2 作者
(23) A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators, The 38th IEEE International Conference on Computer Design (ICCD), 2020, 通讯作者
(24) DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020, 第 2 作者
(25) BitPruner: Network Pruning for Bit-serial Accelerators, PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020, 第 3 作者
(26) CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding, PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), 2020, 通讯作者
(27) Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System, 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), 2020, 通讯作者
(28) Exploring Emerging CNFET for Efficient Last Level Cache Design, 24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019), 2019, 第 4 作者
(29) InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing, 2019 29TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2019, 第 3 作者
(30) Resilient Neural Network Training for Accelerators with Computing Errors, The 30th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, 通讯作者
(31) A Survey on Graph Processing Accelerators: Challenges and Opportunities, JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2019, 第 4 作者
(32) OBFS: OpenCL Based BFS Optimization on Software Programmable FPGAs, In 2019 International Conference on Field Programmable Technology (FPT), 2019, 通讯作者
(33) FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors, 2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018, 第 4 作者
(34) QuickDough: A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay, 2015 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (FPT), 2015, 第 1 作者
发表著作
(1) FPGA overlays. In FPGAs for Software Programmers, Springer, 2016-12, 第 2 作者
(2) Built-in Fault-tolerant Computing Paradigm for Resilient Large-Scale Chip Design, Springer Nature, 2023-05, 第 3 作者

科研活动

   
科研项目
( 1 ) 基于FPGA的专用高能效图计算加速研究, 负责人, 国家任务, 2021-01--2022-12
( 2 ) 面向深度学习处理器的弹性容错技术研究, 负责人, 国家任务, 2021-12--2025-12
( 3 ) 容错深度学习处理器的自动化设计, 负责人, 研究所自选, 2021-06--2023-06
( 4 ) 基于智能存算融合架构的大数据分析和调度框架, 负责人, 国家任务, 2023-01--2024-12
( 5 ) 面向COTS器件的容错深度学习工具链研究, 负责人, 其他任务, 2023-01--2023-12
( 6 ) 芯片设计跨层优化方法, 负责人, 国家任务, 2023-01--2025-12