VLSI, FPGA-accelerated computing , Computer Architecture, SmartNIC, Domain Specific Architectures, Reconfigurable Technology and Systems, DPU, RDMA

Ph.D.  degree  from the University of Science and Technology of China (USTC)

B.S.  degree  from WuHan University 

From 1996 to 2003, he served as an electronics engineer in the 13th research institute of China Electronics Technology Group Corporation and as a SDH R&D system engineer of optical network in HUAWEI company. In 2006 he joined in the institute of Acoustics, Chinese Academy of Sciences. He is currently with the Chinese Academy of Sciences as a professor. His current research interests are fast packet processing, FPGA-accelerated computing, Programmable networks and DPDK. 

[1]Xiaoyong Song, Zhichuan Guo*. Fast_Update_Algorithm_With_Reorder_Mechanism_for_SRAM-Based_Longest_Prefix_Matching_on_FPGA[J].  IEEE Transactions on Circuits and Systems II: Express Briefs,2024,71(1):420-424.

[2]Wang K, Guo Y, Zhichuan Guo*. Highly Concurrent TCP Session Connection Management System on FPGA Chip[J]. Micromachines, 2023, 14(2): 385.

[3] Ke Wang, Yiwei Chang, Zhichuan Guo*. High Performance Network Virtualization Architecture on FPGA SmartNIC[J]. IEICE Transactions on Communications, 2023, 6:500-508.

[4] Xiaoying Huang, Zhichuan Guo*,  Mangu song, FGLB: A fine-grained hardware intra-server load balancer based on 100G FPGA SmartNIC[J],International Journal of Network Management,2022. DOI: 10.1002/nem.2211

[5] Meng Sha, Zhichuan Guo*, Yunfei Guo, Xuewen Zeng.A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform[J], Micromachines, 2022, 13, 1854. 

[6] Meng Sha, Zhichuan Guo*, et al. A High-Performance and Accurate FPGA-Based Flow Monitor for 100 Gbps Networks[J]. Electronics. 2022, 11(1976): 1-16

[7]Luchao han, Zhichuan Guo*,et al. A Multi-Functional Full-Packet Capture and Network Measurement System Supporting Nanosecond Timestamp and Real-Time Analysis[J], IEEE Transactions on Instrumentation and Measurement, 2021,70: 5502712

[8] Xiaoying Huang, Zhichuan Guo*, et al. AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC[J]. Electronics,  2021,10, 1927

[9]Huang, Xiaoying, Guo, Zhichuan*, et al. Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture[J]. IET computers and digital techniques, 2021, 15(6): 427-436

[10] Luchao Han, Zhichuan Guo* , Xuewen Zeng. Research on Multicore Key-Value Storage System for Domain Name Storage, Applied sciences- Basel [J], 2021,11, 7425

[11]Zhao, Jun, Guo, Zhichuan*, et al. High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA[J]. IEEE Communications Magazine. 2020, 58(1): 62-67

已指导学生

韩陆超  博士研究生  081002-信号与信息处理  

董瀚泽  硕士研究生  081002-信号与信息处理  

王慧鑫  硕士研究生  085208-电子与通信工程  

赵然  博士研究生  081002-信号与信息处理  

王昭  博士研究生  081002-信号与信息处理  

黄逍颖  博士研究生  081002-信号与信息处理  

宋锐星  博士研究生  081002-信号与信息处理  

赵军  博士研究生  081002-信号与信息处理  

王可  博士研究生  081002-信号与信息处理  

沙猛  博士研究生  081002-信号与信息处理  

现指导学生

郭云飞  博士研究生  081002-信号与信息处理  

宋晓勇  博士研究生  081002-信号与信息处理  

卢睿  硕士研究生  081002-信号与信息处理  

孙英  硕士研究生  085402-通信工程（含宽带网络、移动通信等）  

常艺伟  博士研究生  081002-信号与信息处理  

潘宜朋  硕士研究生  085402-通信工程（含宽带网络、移动通信等）  

孙泽正  硕士研究生  085402-通信工程（含宽带网络、移动通信等）  

唐成  硕士研究生  081002-信号与信息处理  

张嘉豪  硕士研究生  081002-信号与信息处理  

孙语潜  硕士研究生  081000-信息与通信工程  

赵志翔  博士研究生  081002-信号与信息处理