General
Huawei Li   Professor
State Key Laboratory of Computer Architecture,
Institute of Computing Technology, Chinese Academy of Sciences
 
Email:lihuawei@ict.ac.cn

Research Areas

VLSI/SOC design and test

Approximate computing

Fault-tolerant computing


Experience

   
Work Experience

Oct. 2008- present, Professor, ICT, CAS
Aug. 2009- Aug. 2010, Visiting Professor, University of California at Santa Barbara, USA
Oct. 2001- Oct. 2008, Associate Professor, ICT, CAS
July 2001- Sept. 2001, Assistant Professor, ICT, CAS

Part-Time Positions:
Chair, Fault-Tolerant Computing Technical Committee, China Computer Federation
Adjunct Professor, Xiangtan University
IEEE Senior Member

Teaching Experience
VLSI Testing and Design for Testability
Fault Diagnosis and Reliable Design of Digital Systems

Honors & Distinctions

1. National Technology Invention Award, the State Council of the People's Republic of China, 2012

2. Beijing Science and Technology Award, from Beijing Government, 2014

3. China Quality Technical Award, China Quality Association, 2011
4. Lu Jia-Xi Young Scientist Award, from Chinese Academy of Sciences, 2008
5. Beijing Science and Technology Award, from Beijing Government, 2008
6. Beijing Science and Technology Award, from Beijing Government, 2007
7. Outstanding Science and Technology Achievement (Honor), for my prominent achievement in the Goodson CPU, from Chinese Academy of Sciences, 2003
8. Microsoft Fellowship, from the Microsoft Research, China, 2001
9. Special President Scholarship, from Chinese Academy of Sciences, 2001

Publications

  1. Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” Proc. IEEE 41st International Test Conference (ITC’10), Paper 12.1, Austin, USA, Oct. 2010.

  2. Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test generation for Precise Crosstalk-induced Path Delay Faults,” Proc. IEEE 24th VLSI Test Symposium (VTS’06), Berkeley, CA, USA, May 2006, pp.300-305.

  3. Huawei Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,” Journal of Electronic Testing: Theory and Applications, Vol.21, No.2, 2005, pp.181-195.

  4. Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.

  5. Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.

  6. Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.2, 2012, pp.236-247.

  7. Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.

  8. Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.

  9. Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.

  10. Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.

  11. Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.

  12. Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.

  13. Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.

  14. Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.

  15. Shuangde Fang, Zidong Du, Yuntan Fang, Yuanjie Huang, Yang Chen, Lieven Eeckhout, Olivier Temam, Huawei Li, Yunji Chen, Chengyong Wu, “Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach,” ACM Transactions on Architecture and Code Optimization (TACO), Vol. 11, No. 2, Article 21, June 2014.

  16. Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.

  17. Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Data Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015.

  18. Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.2, pp.285-297, 2016.

  19. Song Jin, Songwei Pei, Yinhe Han, Huawei Li, “A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands”, ACM Trans. Design Autom. Electr. Syst.(TODAES), Vol.21, No.2, Article 27, 2016.

  20. Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors”, IEEE Transactions on Computers, Vol. 65, No.3, pp.716-729, 2016.

  21. Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.3, pp.858-870, 2016.

Research Projects

National Natural Science Foundation of China (NSFC): "Fundamental Theories and Methodologies of Devices for Error Tolerant Computing ", 2015-2019.
National Natural Science Foundation of China (NSFC): "Post-Silicon Timing Validation Considering Delay Variability of Integrated Circuits ", 2012-2015.
National Basic Research Project of China (973): "Efficient Techniques on Design, Verification and Test for Processors", 2005.12~2010.11
National Natural Science Foundation of China (NSFC): "Test generation techniques avoiding overtesting in delay testing", 2008-2010.
National Natural Science Foundation of China (NSFC): "Crosstalk-oriented Delay Testing", 2007-2009
National Natural Science Foundation of China (NSFC): "Hierarchical Methodology for Delay Testing and Timing Analysis in System-on-a-chip", 2002-2004.
National High-Tech Project of China(863): "Security Testing and Evaluations of Trusted Computing Platforms", 2007-2009.
National High-Tech Project of China(863): "Design of Concurrent, Multi-thread and Configurable Network Processors", 2003-2005.

Conferences

General Co-Chair, IEEE 23rd Asian Test Symposium (ATS), Nov. 2014, Hangzhou, China
Topic Coordinator in Program Committee, 43rd and 44th IEEE International Test Conference (ITC'12/13, Anaheim, USA, Sept. 2012/2013)
TPC Subcommittee Chair for Track Test and DFT, 18th IEEE Asia and South Pacific Design Automation Conference (ASP-DAC'13, Yokohama, Japan, Jan. 2013)
Program Co-Chair, IEEE 16th Asian Test Symposium (ATS), Nov. 2007, Beijing, China  ​
Program Chair, IEEE 4th Workshop on RTL and High-Level Testing (WRTLT), Nov. 2003, Xi’an, China 
Program Chair, 4th China Test Conference, August 2006, Beidaihe, China 
Program Co-Chair, 3rd China Test Conference, Oct. 2004, Changsha, China 

Program Committee Member, in:
    ITC: IEEE International Test Conference
    ASP-DAC: IEEE Asia and South Pacific Design Automation Conference
   ETS: IEEE European Test Symposium
   ATS: IEEE Asian Test Symposium
   ISVLSI: IEEE Computer Society Annual Symposium on VLSI
   DFT: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
   VLSI-DAT: International Symposium on VLSI Design, Automation and Test
   APCCS: IEEE Asia Pacific Conference on Circuits and Systems
   VDAT: VLSI Design and Test Symposium